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Here is my code for 4 to 1 mux:

entity a is
Port ( a : in STD_LOGIC;
       b : in STD_LOGIC;
       c : in STD_LOGIC;
       d : in STD_LOGIC;
       contr : in STD_LOGIC_VECTOR (1 downto 0);
       z : out STD_LOGIC);
       end a;
end a;

architecture Behavioral of a is

begin
 with contr select
 z <= a when "00",
 b when "01",
 c when "10",
 d when "11",
 '0' when others;

 end Behavioral;

But I've seen that this code is also written with a signal declaration:

 entity a is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           c : in STD_LOGIC;
           d : in STD_LOGIC;
           contr : in STD_LOGIC_VECTOR (1 downto 0);
           z : out STD_LOGIC);
           end a;

          architecture Behavioral of a is
signal control_signal : std_logic_vector (1 downto 0);
begin
control_signal <= contr;
with control_signal select
z <= a when "00",
     b when "01",
     c when "10",
     d when "11",
     '0' when others;

end Behavioral;

So what's the difference between these two? When and why should I use signals?

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    \$\begingroup\$ As soon as I see z or x as signal name in an HDL design, I conclude that an amateur has been busy. I would then ignore the rest of the code. \$\endgroup\$
    – Oldfart
    Apr 23, 2020 at 15:18
  • \$\begingroup\$ @Oldfart I don't see any reason why not to in this design. This is not anything serious. \$\endgroup\$ Apr 23, 2020 at 15:27

3 Answers 3

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There is no practical difference. Synthesis will remove the signal and the final circuit and firmware from the two will be identical.

They version without the signal is the preferred design because it is clearer and simpler.

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I think clock domain synchronization if contr is asynchronous to the FPGA clock. Standard practice to reduce metastability of asynchronous signals is to feed it through a chain of flip flops prior to usage by anything synchronous.

But the entire code chunk is not clocked to begin with so I do not see why you would actually need that here since it just adds latency. But this is something you need to be aware of which goes unmentioned when starting out on FPGAs so I will throw it in.

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This is just creating as signal that is an alias for another signal name. Sometimes the signal name in the port list is not very intuitive and makes the code easier to read. On the other hand, having to know that there is an alias can also lead to confusion.

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