How to Prevent CD4017 from Resetting to Random Count on Power On

Question

I'm working on a project using a couple of CD4017 decade counter chips sharing a clock signal from a 555 oscillator.

The ideal behavior I would expect is that the chips would all start on count 0 when given power. They do this most of the time but sometimes they start on a completely random count and the synchronization between the chips is thrown off. I've tried to get around this by putting a capacitor on the reset pin of the 555 and the enable pins of CD4017s like so. This adds a small lag between the 555 clock being enabled when the device receives power, and a small lag for the CD4017 clock inputs being enabled.

However, the CD4017s still start on a random count occasionally when given power. Is there any standard, cleanish method I can use to assure they all power on to count 0?

I'm sure I could figure out something hacky with the but I'm trying to keep a low part count.

Answer 1

Try this: The capacitor will force the reset for a few hundreds of microseconds after power up. Also: Add a large capacitor (can be electrolytic) at the power terminal of the board, and a 1uF at each Vcc pin on every ic.

The reset pin must be connected to ground with a pull down resistor (R1) or set either high or low from an external input (Master Reset). It can't be left floating.

^{simulate this circuit – Schematic created using CircuitLab}

Answer 2

The best (and most bulletproof) solution is to use a reset chip such as an ADM810. Suitable voltage ranges are available for 3.3V and 5V rails. If you have a different supply you may have to use a different supervisory chip that has resistor-programmable voltages. The below shows the functionality (the ADM810 has active-high output rather than the more commonly required active low shown in the diagram):

When the voltage level drops below the lower threshold the reset signal is asserted for a minimum of 0.24 second. It is not released until the supply voltage is higher than the upper threshold for a minimum of 0.24 second. You should pick threshold voltages that guarantee proper operation at the lower threshold meaning it will operate down to the lower threshold and will always be reset properly.

You may also need to put some resistance across the power supply to cause it to reset reasonably quickly rather than retain the previous state. Sometimes a fancier kind of clamp is used in special situations.

The R-C kind of reset is sometimes used in low end consumer products where it's acceptable for it to fail once in a while (the user will just manually cycle the power), but it's a very poor substitute for a proper circuit.

Answer 3

The solution I found is this. Turns out it is necessary to use the capacitor reset method for synchronization. Diodes are also necessary to prevent a conflict between the pin reset output levels and the capacitor reset. I've breadboarded this and it's working well, very consistent where nothing else has been: