# Is it necessary to declare reg before assignment in Verilog?

Is it necessary to declare reg before assignment in Verilog? Or does Verilog-2001 allow to declare reg after assignment?

For example this code is synthesized by Quartus and simulated by ModelSim without errors

module my_module(output out_my_reg);
reg my_reg;
assign out_my_reg = my_reg;
endmodule


And this code is synthesized by Quartus without errors but in ModelSim its simulate leds to an error Undefined variable﻿: 'my_reg'

module my_module(output out_my_reg);
assign out_my_reg = my_reg;
reg my_reg;
endmodule


The LRM says in 1800-2017 section 6.5 Nets and variables that you must declare data(signals) before using them. There are such things as implicitly declared nets, but that does not apply here. There are also different rules when referencing names that have a . (period) in them. But both of those other situations contribute to why Verilog has this rule.