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I'm designing a circuit that contains an AD5206 digital potentiometer. I'm using a single 5V supply and the IC has both GND and VDD pins tied to ground.

The data sheet does not make any recommendations for decoupling capacitors and specifies a maximum current draw of only 60 uA (avg. is 12 uA).

Is this current draw so low that decoupling is not required or should I add a 100n decoupling capacitor on the VCC pin?

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2 Answers 2

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When you load values into the chip's registers via the serial input, your digipot will behave like any other logic chip and draw current spikes from the supply, so it should have the same decoupling requirements as say, a bunch of logic gates of the same speed grade.

Once the data is loaded though, it won't do much and probably only draw some leakage current.

So I'd say add the usual decoupling cap, pick the same value you use on the other chips around, no need to add a BOM item just for this.

If you have a decoupling cap nearby for another chip, like a few cm away, it will probably be enough. But it is better to put the capacitor footprint and not populate it, than not put the footprint and realize later it is needed...

Note if you use positive and negative supplies, each needs a decoupling cap.

Also, since the internal FET switches capacitance will couple some power supply noise into the output of your potentiometer, you can use the local decoupling cap as a filter. Simply add a resistor in the supply line, it draws very little current so even 1 kOhm should work. Then the local 100nF cap will get rid of HF power supply noise.

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Current draw being low has nothing to do with decoupling. Decoupling is to deal with the detrimental effect trace inductance has when rapid changes in current demand occur. 60uA peak and 12uA average are both small, but that is a 500% change. It doesn't matter that they are both low numbers because if that change happens fast enough...

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