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schematic [The small signal circuit]

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Hey, so in this circuit i already figured out the input and output impedance without R1, easy stuff... But now i want to know them with R1 included.

For the input i want the impedance with R1 and R4 , using small signal mode (hybrid-pi model) i'm not sure what to do. For the output R4 is not included.

What advice you guys can give me?

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  • \$\begingroup\$ The way to determine an input impedance is to install a current source \$I_T\$ across the input which will generate a voltage \$V_T\$. Express \$V_T\$ as a function of \$I_T\$ and the ratio \$\frac{V_T}{I_T}\$ is your input resistance. I answered the question last time here with the extra-element theorem or EET and you already have half of the answer. You can follow the steps I described in my reply. \$\endgroup\$ – Verbal Kint Apr 24 at 15:49
  • \$\begingroup\$ I actually solved it using the superposition theorem but yours was also very useful for me because i never heard of EET before. \$\endgroup\$ – G0tBlackOps Apr 24 at 15:52
  • \$\begingroup\$ This is good then, another opportunity to acquire the skill! : ) \$\endgroup\$ – Verbal Kint Apr 24 at 15:54
  • \$\begingroup\$ Verbal K. is far better than I on the theoretical analysis, whereas I share my secrets for practical design philosophy and demonstrated by simulation leaving a lot of explanation out in order for you to ask specifics. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Apr 24 at 16:53
  • \$\begingroup\$ Thank you for the laudatory words Monsieur Stewart : ) I'll see if time permits for an analysis tomorrow. \$\endgroup\$ – Verbal Kint Apr 24 at 18:37
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You can determine the input resistance offered by the circuit after the dc-block capacitor \$C_1\$ by using the extra-element theorem or EET already applied in this answer. The extra element is still the feedback resistor \$R_1\$ that I call \$R_f\$ in my calculations.

I am going to first determine the input resistance when \$R_f\$ is set to infinity or simply removed from the circuit. How do you determine a resistance or an impedance from a connecting port? You install a test generator \$I_T\$, the stimulus, which is going to generate a voltage \$V_T\$ across its terminal, the response. Express \$V_T\$ as a function of \$I_T\$ to obtain the ratio you want which is \$\frac{V_T}{I_T}\$.

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The input resistance in this mode (you look at the upper right sketch) is obtained quickly as \$I_T\$ imposes the base current.

Then, you turn the excitation off (open-circuit the current source) and determine the resistance offered by \$R_f\$s terminals in this mode. A few lines of algebra and you have it.

Finally, you null the response and determine the resistance offered by \$R_f\$s terminals in this mode. You are looking at the right low-side sketch. The cool thing of nulling the voltage across a current source (this is the response from the beginning) is that it becomes a degenerate case: you can replace it by a short circuit. If you do that, the base is grounded, the base current disappears and all what is left is the collector resistance. We say the null propagates and by inspection, \$R_n=R_C\$.

This is it, we can now assemble all the pieces according to the EET: \$R_{in}=R_{inf}\frac{1+\frac{R_n}{R_f}}{1+\frac{R_d}{R_f}}\$. This is what I have done in the below Mathcad file with arbitrary values. What is cool is that you can verify all your intermediate steps by looking at the dc bias points via a quick SPICE simulation:

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If you look at the result I found analytically - please note the low-entropy form meaning a well-arranged formula - it exactly matches that of the SPICE simulation. You can then add the other resistance in parallel with \$R_C\$ if you want, \$R_4\$ in your circuit. Voilà !

Addendum:

While enjoying the view on the Pyrenees this morning, I looked at the output resistance. Nothing insurmountable with the help of the EET once more. The circuit is shown below where the input capacitor isolates the source from the transistor for \$s=0\$:

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First, you install the test generator \$I_T\$ across \$R_C\$, the port at which you want \$R_{out}\$. The circuit is that of the upper right corner and you see that in absence of \$R_f\$, there is no base current and \$R_C\$ remains alone: \$R_{inf}=R_C\$.

Then, open-circuit the test generator and determine the resistance \$R_d\$ "seen" from \$R_f\$'s connecting terminals. We can reuse the calculation already done for the input impedance where we found \$R_d=r_{\pi}+(\beta + 1)(R_E+R_C)\$.

Final lap, determine the resistance \$R_d\$ "seen" from \$R_f\$'s connecting terminals when the current source is shorted or when its response is nulled. This is a null double injection or NDI. The equation to determine the resistance is the first equation used in determining \$R_d\$ because node c is conveniently grounded. This is it, we have all we need to assemble the pieces and unveil the output resistance:

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You can check the calculations with the dc bias points and that is a convenient way to chase mistakes. Finally, I can simulate the entire circuit and use a .TF SPICE statement to obtain the output resistance:

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The EET is part of the fast analytical circuits techniques or FACTs that I described in the book I wrote on the subject. The idea is to split a complicated circuit into smaller pieces you can individually solve and check. That is the strength of the approach which, at the end, leads to a well-organized expression where each contribution is clearly seen.

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to solve this with considering R1 you need to use miller theory or also you can solve this with KVL and KCL as well

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  • \$\begingroup\$ How should i use KVL and KCL in this situation? \$\endgroup\$ – G0tBlackOps Apr 24 at 15:35
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-Vcc + (R2 . I1) + (R1 . I1/B) + Vbe + R3.(I1 * (B+1)/B)=0

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    \$\begingroup\$ Can you rationalize your two answers into one? \$\endgroup\$ – Andy aka Apr 24 at 15:58
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    \$\begingroup\$ You need to edit your previous answer... Unless you are providing two completely different solutions, there's no need to have this answer. \$\endgroup\$ – KingDuken Apr 24 at 16:21
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You know that if the single transistor amp was an Op Amp \$r_i=0, r_{01}=0 \$ because of high excess Aol gain above the desired closed-loop gain of \$ Av(f) = R1/(Z_{C_1}(f)\$.

Since the open-loop gain will be something on the order of 1e2 instead of 1e6 the impedance values are raised to include the sources as the negative feedback going from 1e2 to 1e1 =10 is only a feedback gain of 10.

But your thinking should be that C1 define the minimum input impedance and ought to have a series Rs to achieve a linear frequency gain of -R1/Rs somewhere around -10 to -20 with distortion and asymmetry reduction reduces by the square of this feedback gain Beta, so 10% THD can be reduced to 0.1% with a gain of 100 reduced to 10 with NFB.

I attempted to show your target gains and effective impedance with hand waving arguments for simplicity, yet practical optimums.

The amplifier source impedance will affect Zin with C1 and R1 will reduce the gain as well so this ought to be at least 10x the driving source.

Any questions?

Simulation

Design Specs: Aol >=100, Acl =40 Zin = 15k Zout = 50k (Zout~R2*Acl/Aol)

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If you pull the 50k dummy load, you will see a closed-loop gain of 41. But notice that this dummy load has asymmetry due to the low feedback gain or low ratio = open/closed loop = 100/40=2.5. So there is a huge tradeoff for distortion reduction with this high gain, which is why a closed-loop gain of 10x is far better for THD yet that will reduce Zin,out accordingly.

Also Please Note, I chose to DC couple the input selecting the optimum pullup R for the balanced output. The results are indicated on the schematic and fairly independant of hFE but selected for gain and supply voltage.

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