# Why the voltage across MOSFET (VDS) is increasing even when the voltage at the gate (VGS) is constant?

Following is the screenshot schematic for Buck-derived half-bridge isolated DC-DC converter in LTSpice.

In the following plot it can be seen that when the lower switch is turned off the voltage across it (purple) rises to a maximum value and it makes sense because the voltage across a switch is maximum in the off state. When the upper switch is turned on then voltage across it starts rising (yellow), but the voltage across a switch is zero (minimum) when it is in on state. At first I think that this rise in VDS is due to decrease in the Vg as the boot strap capacitor is discharging. But when I plotted the VGS (green) it is essentially constant well above the threshold value. My question is how the VDS can change if VGS is constant? Also why the voltage across the upper switch (with VGS=0V) changes to zero when the lower switch is turned off as highlighted on the plot?

Inductances are calculated using the relation $$\\ sqrt(L_p/L_s)=1/n)\$$ where n is the turn ratio I assumed Ls to be 1uH and then Lp is found

Here are the associated simulation files