The following is based on the NMOS version of the circuit.
It applies equally to PMOS versions with polarities adjusted accordingly.
Note that Kyle B, with very large experience, never uses the protection that I would include almost of right. He is undoubtedly correct in his choice as his applications apparently never deliver the transients or oscillations that matter. In general situations or if in doubt, my approach is safer, at the small extra cost and PCB area required.
Based on long experience:
PROTECTING SWITCHING MOSFETS AGAINST MURPHY
I will always add D43 - with zener voltage set to clamp Vgs at some value below Vgs_max and above Vgs_drive_max, unless the design is extremely cost sensitive and it is absolutely certain that D43 is not needed.
D43's role is to ensure that Vgs never exceeds Vgsmax - which condition is usually fatal to the FET. The usual source of excess Vgs is from Millar coupling of drain transients to the gate. These will usually only be present for inductive loads. If it is absolutely certain that there will never (ever ever) be inductive load components D43 can be notionally omitted - but Murphy knows some good tricks.
I once had a high volume application where the FET would die within a few minutes of operation without D43, and last indefinitely with it installed. The load was an open wire nichrome resistor with some but low inductance. In practice enough to make a huge difference.
D42 is not usually needed. If it is needed there are better solutions.
Negative Vgs swing for an N Channel MOSFET is not usually either damaging or performance affecting, except when it is part of an oscillatory waveform.
Under some gate drive conditions ringing occurs due to interaction and reflections between gate and driver.
The first and usual response is to always include a small value resistor (often 1 to 10 Ohms) between driver and gate. This will help dissipate gate oscillations. It will also slightly slow peak gat currents thus softening rising edges, thereby reducing EMI and switching losses.
A useful solution if gate oscillation is a problem is to mount a usually reverse biased small Schottky diode gate to source, physically mounted as close to the FET as reasonably possible. This diode will conduct on negative gate oscillatory excursions and rapidly remove energy from an oscillating gate.
A final "trick" which is not a clamp per se but which can be handy 'in extremis' and which should be considered on a a case by case basis, is to add a ferrite bead on the drain lead of the MOSFET. For TO220 and similar packages this can usually be done with no other mechanical or electrical changes. This has an effect on drain transients - possibly adversely so in high bandwidth circuits. Results will vary with material used. Not often required.
You mentioned that: D42 is not usually needed. If it is needed there are better solutions. what situations is D42 needed and what are the better solutions?
In the original circuit D42 is there to clamp negative gate excursions.
As negative gate swing is not useful you can either ignore it if it is causing no harm, or address the cause, or eliminate it more surely.
The series gate drive resistor addresses ringing prevention and damping.
The gate-source connected reverse Schottky physically close to the FET stamps on the negative excursions far more surely than a D42 zener would.
Note that the D43 zener and the new D42 - now a usually reverse biased Schottky - are now in parallel and not in series as in your case.