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Is clamping the gate and source of a MOSFET really important? I have seen this in some articles and some datasheets of MOSFETs where they have built in clamping.

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As far as i know they are used for ESD. Asuming that the gate is just a trace to a controller device I don't see potential danger of an ESD especially when the cicuit you are going to build on has a case.

So do I need them? Are they critical?

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    \$\begingroup\$ On top of ESD, Miller capacitance can also be a reason. \$\endgroup\$
    – winny
    Apr 25, 2020 at 7:02
  • \$\begingroup\$ Battery reverse polarity protection circuits \$\endgroup\$
    – Andy aka
    Apr 25, 2020 at 7:53
  • \$\begingroup\$ @Andyaka for application where everything is fixed, then it is not needed? \$\endgroup\$
    – Jake quin
    Apr 25, 2020 at 8:08
  • \$\begingroup\$ @winny thats a new term for me, from what i understood at skimming articles is basically an overshoot in voltage when transistioning states? which would make perfect sense for where you want to use clamping \$\endgroup\$
    – Jake quin
    Apr 25, 2020 at 8:12
  • \$\begingroup\$ If the supply voltage is used to derive the gate signal AND it is higher than the gate-source breakdown voltage then, you use gate-source protection such as a zener. Similarly with a BJT, if the base current might be too high then a current limiter (aka resistor) is used. \$\endgroup\$
    – Andy aka
    Apr 25, 2020 at 8:12

2 Answers 2

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The following is based on the NMOS version of the circuit.
It applies equally to PMOS versions with polarities adjusted accordingly.

Note that Kyle B, with very large experience, never uses the protection that I would include almost of right. He is undoubtedly correct in his choice as his applications apparently never deliver the transients or oscillations that matter. In general situations or if in doubt, my approach is safer, at the small extra cost and PCB area required.

Based on long experience:

PROTECTING SWITCHING MOSFETS AGAINST MURPHY

I will always add D43 - with zener voltage set to clamp Vgs at some value below Vgs_max and above Vgs_drive_max, unless the design is extremely cost sensitive and it is absolutely certain that D43 is not needed.

D43's role is to ensure that Vgs never exceeds Vgsmax - which condition is usually fatal to the FET. The usual source of excess Vgs is from Millar coupling of drain transients to the gate. These will usually only be present for inductive loads. If it is absolutely certain that there will never (ever ever) be inductive load components D43 can be notionally omitted - but Murphy knows some good tricks.

I once had a high volume application where the FET would die within a few minutes of operation without D43, and last indefinitely with it installed. The load was an open wire nichrome resistor with some but low inductance. In practice enough to make a huge difference.

D42 is not usually needed. If it is needed there are better solutions.
Negative Vgs swing for an N Channel MOSFET is not usually either damaging or performance affecting, except when it is part of an oscillatory waveform.
Under some gate drive conditions ringing occurs due to interaction and reflections between gate and driver.
The first and usual response is to always include a small value resistor (often 1 to 10 Ohms) between driver and gate. This will help dissipate gate oscillations. It will also slightly slow peak gat currents thus softening rising edges, thereby reducing EMI and switching losses.

A useful solution if gate oscillation is a problem is to mount a usually reverse biased small Schottky diode gate to source, physically mounted as close to the FET as reasonably possible. This diode will conduct on negative gate oscillatory excursions and rapidly remove energy from an oscillating gate.

A final "trick" which is not a clamp per se but which can be handy 'in extremis' and which should be considered on a a case by case basis, is to add a ferrite bead on the drain lead of the MOSFET. For TO220 and similar packages this can usually be done with no other mechanical or electrical changes. This has an effect on drain transients - possibly adversely so in high bandwidth circuits. Results will vary with material used. Not often required.

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You mentioned that: D42 is not usually needed. If it is needed there are better solutions. what situations is D42 needed and what are the better solutions?

In the original circuit D42 is there to clamp negative gate excursions.
As negative gate swing is not useful you can either ignore it if it is causing no harm, or address the cause, or eliminate it more surely.

The series gate drive resistor addresses ringing prevention and damping.

The gate-source connected reverse Schottky physically close to the FET stamps on the negative excursions far more surely than a D42 zener would.
Note that the D43 zener and the new D42 - now a usually reverse biased Schottky - are now in parallel and not in series as in your case.

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  • \$\begingroup\$ I noticed that you only mention on the NMOS does this apply for PMOS as well ? (D45). \$\endgroup\$
    – Jake quin
    Apr 25, 2020 at 10:31
  • \$\begingroup\$ @Jakequin Yes. Near the end I say "Similarly for the P Channel equivalent situations." -> I'll move that to near the top and make it clearer. \$\endgroup\$
    – Russell McMahon
    Apr 25, 2020 at 10:32
  • \$\begingroup\$ Apologies, i seem to have missed that. My current project does involves inductive load and im trying to build to make it last, You mentioned that: D42 is not usually needed. If it is needed there are better solutions. what situations is d42 needed and what are the better solutions? \$\endgroup\$
    – Jake quin
    Apr 25, 2020 at 10:42
  • \$\begingroup\$ @Jakequin The following text covers that. D42 is there to clamp negative gate excursions. As negative gate swing is not useful then you either ignore ir if it is causing no harm, or address the cause, or eliminate it more surecly. The series gate drive resistor addresses ringing prevention and damping. The gs reverse Schottky physically close to the FET stamps on the negative excursions far more surely than a D42 zener would. Note that the D43 zener and the D42 - now a reverse Schottky, are now in parallel and not in series as in your case. \$\endgroup\$
    – Russell McMahon
    Apr 25, 2020 at 10:46
  • \$\begingroup\$ Apologies again i seem to be not connecting things properly today. Yes i always place a gate resistor, i have learned that from a previous question. The FETS gates seem to tolerate negative voltage very well, if a negative gate(especially on NMOS) exceeds its capabailities, then i have greater problems in my hands as for sure that voltage will start destroying ICs. \$\endgroup\$
    – Jake quin
    Apr 25, 2020 at 11:44
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Like everything else in life the answer is: It depends

Depends on the nature of the circuit (does it have highly inductive switching loads? Is it 'life-critical', or is it a McDonalds happy meal toy? Or is it the fuel regulation control for a 737 jet??) etc..

MOSFETs work just fine without them

My company makes consumer products by the 100's of thousands. We use millions of 2-cent MOSFETs. Everything is battery operated. There's no known significant issues we've ever had with MOSFETs failing. We never use those protections

If I were making electric cars, I'd have these protections on my motor controls.

So... It depends

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    \$\begingroup\$ For a guy who have no field experience, I cant guage of how critical those protections are, i dont have the numbers for parts thats worked to parts that failed without them. But i would like to design with adequate protection, not as low as happy meal toy yet not as high as controls for a 737 jet. I will most likely use what i will learn from this question to mosfets used to switch inductive loads (relays,solenoids) and would like to design it to have the same robustness as a good computer motherboard \$\endgroup\$
    – Jake quin
    Apr 25, 2020 at 8:15

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