I would like to know where does differential noise come from in an SMPS. I understand where the common mode noise comes from. It mainly comes from the fact that there is capacitance between switching voltage node and ground earth. I understand that it is noise as this input current for charging/discharging the capacitances is useless for the purpose of the SMPS. In other words, if there were no capacitances it will still work. I m not considering here the input noise that could come from external environnement. I consider that the SMPS is working in a perfect environnement without noise.

In the other hand, I have some troubles to understand where the differential noise comes from. I have a book "Switching Power Supply A to Z" from Sanjaya Maniktala (nice book !) which tells that the DM noise generator is the voltage ripple caused by the ESR of the smoothing capacitor. Here is the model : enter image description here

Here is the extract about ESR :

enter image description here

It is true that the ESR of the capacitor modify slightly the voltage across the smoothing capacitor. And if it modified it seems logical that the current drawn by the transformer (for example) will not be the same as if there were no ESR. So at this point, I though the noise where coming from here.

I did a simulation (simulation with no ESR and a simulation with ESR and parasitic parallel capacitance across the diode rectifier as when the frequency increase some current drawn by the SMPS can be seen at the input). My simulation may be bad...

Perfect model (ie without source of noise): enter image description here

Model with source of noise: enter image description here

Here are the settings : enter image description here

Here are the results : enter image description here

And finally I did an FFT of the two different currents : (Warning with the colors !!!) enter image description here

An other view : enter image description here

As a conclusion, I see that the ESR is introducing noise at frequencies higher than 100 KHz (switching frequency) but it tends to lower the "noise" at lower frequency. What does it mean ? Is it normal ? Is the 2 spectrums have the same energy ? In other words, does the higher frequency current replace the lower frequency current ? In this case, how could we consider it as noise ? In my mind, noise is something which is useless (at least in this application).

What do you think about the fact that the ESR is introducing noise ? and what about the parasitic parallel capacitors of the diodes ? When I tried to see the influence of the parasitic parallel capacitor (10nF @ a switching frequency of 100 KHz) with a model with a 1 Ohm ESR. By comparing a model with and without a parallel parasitic capacitor, I clearly see nothing significant.

Thank you very much and have a nice day :)

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    \$\begingroup\$ Your model has too much complexity and it clouds the issue - it can be modeled by assuming the supply is perfect DC feeding via 50 uH and that there are no rectifiers involved. This is how noise is measured in practice - using a LISN - such as this one. try modeling like this and cut out all the stuff that clouds the basic problem. \$\endgroup\$
    – Andy aka
    Commented Apr 25, 2020 at 10:21
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    \$\begingroup\$ See also this question about how to use a LISN in a simulator. \$\endgroup\$
    – Andy aka
    Commented Apr 25, 2020 at 10:24
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    \$\begingroup\$ You can also have a look at the How2Power newsletter which features an article on this subject. By the way, it is important to properly size the analysis window in SPICE with the correct .TRAN parameters to match or approach those of the spectrum analyzer. I published an article in EDN in 1996 about this. \$\endgroup\$ Commented Apr 25, 2020 at 10:37
  • \$\begingroup\$ As usual thank you for your links ! I will take a look on it ! I do not know how I would do without you ! \$\endgroup\$
    – Jess
    Commented Apr 25, 2020 at 10:45
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    \$\begingroup\$ Minor nitpicks: even if you want to work with idealized components, there's no need to tempt the timestep too small devil (or siblings). Try to avoid Vfwd=0 for diodes (while making use of ron/epsilon/revepsilon, if possible, see manual for why), and setting a negative hysteresis for VCSW can go a long way. Also, C5 and C2 (upper side of the bridge) are not connected the way you probably want. And even a poor ideal MOSFET might need an antiparallel diode. Having said these, I agree with the comments above, unless you're looking for a more in-depth answer. \$\endgroup\$ Commented Apr 25, 2020 at 11:10


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