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From various chip manufacturer articles and other post in this site, I still have doubts on my circuit for switching inductive loads.

I have two setup here that both switches an inductive but using diferent MOSFET one is a P-Channel and the Other is N-Channel. A zener diode is placed on the Gate and source of both, the value for this zener is calculated to be greater than your typical Vgate voltage and less than the Fets Maximum Vgs rating.

The best suppression for inductive seems to be a Schottky and zenner parrallel to the inductive load. Schottkey should atleast handle the full current of the inductor (1A to 2A which is pretty common). For the Zener selection is seems to be geater than supply voltage yet less than the fets Vds(max).

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As for my questions:

  • When the coil collapses, are there danger of the current going back through the mosfets?
  • For the NMOS setup in blue line is there danger of it going back to the power rails? I do not want to stress my PMICs
  • For the PMOS is that ground safe to be connected directly to the logic grounds? I would like the setup to be able to have an alternate function where it can power digital ICs where having the same ground is important
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  • \$\begingroup\$ D1 is the wrong way round. The MOSFET will never turn on properly. Was this intentional? Correspondingly R3 would likely need to be a few kohm too. \$\endgroup\$
    – Andy aka
    Apr 25, 2020 at 13:54
  • \$\begingroup\$ Is a gate drive driving these MOSFETs or is something else like an I/O pin? If it’s an I/O And a logic level mosfet then I agree with Andy aka to use higher gate resistance. \$\endgroup\$
    – Leoman12
    Apr 25, 2020 at 13:57
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    \$\begingroup\$ For the Zener selection is seems to be geater than supply voltage yet less than the fets Vds(max). - NO - the zener voltage plus the maximum supply voltage should be less than Vds(max) - I wouldn't go closer than two-thirds either. \$\endgroup\$
    – Andy aka
    Apr 25, 2020 at 13:57
  • \$\begingroup\$ The diode doesn't need to be anything special either and certainly doesn't need to be a schottky especially as they have high leakage current and this application doesn't require high speed at all unless you are using fast PWM. (I assumed a relay coil BTW). \$\endgroup\$
    – Andy aka
    Apr 25, 2020 at 13:59
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    \$\begingroup\$ Gate voltage cannot drop more than 0.7 volts below source voltage - as I said right at the top of this comment thread: D1 is the wrong way round. Think about it!!! \$\endgroup\$
    – Andy aka
    Apr 25, 2020 at 14:45

1 Answer 1

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When the coil collapses, are there danger of the current going back through the mosfets?

Yes there is. It's a certainty that current will flow into the parasitic capacitance of the MOSFET and, although less certain, if dv/dt is fast enough, it can raise the gate voltage sufficiently (via internal capacitive coupling) and reactivate the MOSFET temporarily. This happens quite commonly.

For the NMOS setup in blue line is there danger of it going back to the power rails? I do not want to stress my PMICs

Bearly anything at all will happen here. Because the MOSFET drain source capacitance is real (as previously mentioned) the flyback current passing through the zener is slightly egged into pushing a little current back into the supply due to that capacitance but, it is a minor, minor problem.

For the PMOS is that ground safe to be connected directly to the logic grounds? I would like the setup to be able to have an alternate function where it can power digital ICs where having the same ground is important

Similarly to directly above there can be a small injection of charge but, providing the ground plane is good, it won't be noticed. As with either (2) and (3) keep the zener/diode close to the inductors.

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  • \$\begingroup\$ As to answer(1). and my guess to solve this problem is to add another diode at the gate blocking the current from reactivating the FET? \$\endgroup\$
    – Jake quin
    Apr 25, 2020 at 14:22
  • \$\begingroup\$ @Jakequin no that won't work - it happens internally and the best you can do is clamp the gate-source voltage (when not required to be activated) to some voltage close to 0 volts. However, it is an extreme example I'm quoting and only really happens on high voltage supplies with fast dv/dt. \$\endgroup\$
    – Andy aka
    Apr 25, 2020 at 14:27

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