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This is with regard to a series of my ESD and Inrush Related questions.

My circuit :

enter image description here

The Node A goes to two other circuits like below :

enter image description here

AND

enter image description here

Now, I apply an ESD pulse of say 8kV/330pF, the capacitors C0001, C0002, C0003 and C0004 have the ability to clamp down the voltage to a certain amount.

But now, I need to ensure that whether that voltage does not exceed the maximum ratings of downstream devices like D0004 and MOSFET Q0001 and other components which are connected to NODE A.

In the D0004 Zener 6.2V rated datasheet, only the absolute maximum ratings are provided for Power Dissipation. There is no maximum rating which indicates the maximum voltage that the zener diode can handle. How to deal with this case?

The same I see for MOSFET BSP317P. Only Max Vds. So, I can take that the maximum voltage that the source terminal can handle is 250V with respect to the drain. If the output voltage is 25V, the MOSFET source terminal can handle a maximum of 225V approx theoretically. Is this correct?

And for the other two transistors (BC807 & BC817), the maximum collector emitter voltage is 45V.

So, I see that the ESD Capacitors should be able to clamp the ESD pulses to less than 45V. If it does, then our components are safe. Correct?

My questions :

  1. Are my above understandings correct?

  2. How to find the Absolute maximum Voltage rating of the Zener diode?

  3. And if the output voltage is connected as a regulator input, should I also check the maximum rating of the regulator too? As the ESD pulse is of very short during, the Zener D0004 may not have enough time to clamp it. But will the MOSFET allow this voltage to affect the downstream circuits connected to Output voltage?

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  • \$\begingroup\$ This question you raised yesterday is very related - the answer I gave yesterday allows this question to be simply answered. The only difference I see is that yesterday it was 4 kV and 150 pF but today it's 8 kV and 330 pF. \$\endgroup\$ – Andy aka Apr 25 at 17:17
  • \$\begingroup\$ I couldn't get you. Suppose for an ESD Spec of +8kV & 330pF, The Clamp voltage would be = (8kV * 330pF)/47nF = 56.17V. So, this voltage might damage the two transistors (BC807 & BC817) , right? \$\endgroup\$ – Newbie Apr 25 at 17:23
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    \$\begingroup\$ The circuits that you say are connected to node A, are floating. Please draw a complete circuit, show where the remaining wires are connected to. \$\endgroup\$ – Huisman Apr 25 at 17:23
  • \$\begingroup\$ @Huisman , Yes. I just want to understand whether the components connected to Node A, would get affected by the ESD pulse. Is my methodology for checking the Max Vce of Transistors with the Max Clamped ESD pulse correct? \$\endgroup\$ – Newbie Apr 25 at 17:25
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    \$\begingroup\$ @newbie - yesterday you asked for theoretical confirmation of your calculations and I did that - surely me confirming what you calculated and you now saying "I couldn't get you" are contradictory. \$\endgroup\$ – Andy aka Apr 25 at 17:30
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In the D0004 Zener 6.2V rated datasheet, only the absolute maximum ratings are provided for Power Dissipation. There is no maximum rating which indicates the maximum voltage that the zener diode can handle. How to deal with this case?

Zener diodes don't have a maximum voltage rating for the obvious reason of the Zener effect. Zener diodes tend to stay close to their Zener breakdown voltage. The phenomenon that may destroy a Zener diode is overheating due to overcurrent.

In your application, D004 will clamp the Vgs of Q0001 to about 6.2V in case of an ESD pulse.

The same I see for MOSFET BSP317P. Only Max Vds. So, I can take that the maximum voltage that the source terminal can handle is 250V with respect to the drain. If the output voltage is 25V, the MOSFET source terminal can handle a maximum of 225V approx theoretically. Is this correct?

The reasoning is correct. But I don't see what this voltage rating has to do with the ESD pulse. In case of a positive ESD pulse, with the 47nF capacitors failing, if there were enough energy in the ESD pulse, D0004 would turn on the mosfet. The remaining energy of the pulse (if there would be left) would cause a small voltage drop across the conducting mosfet. In case of a negative ESD pulse, with these 47 nF capacitors failing, the body diode would just conduct.

And for the other two transistors (BC807 & BC817), the maximum collector emitter voltage is 45V.

As commented, these circuits are floating now. I depends how they are connected to ground, assuming the ESD pulse is applied with respect to ground.
Moreover, your schematic shows R2105 is 0 Ω, meaning it shorts Q2102 and neither ESD nor any other voltage will affect Q2102...

So, I see that the ESD Capacitors should be able to clamp the ESD pulses to less than 45V. If it does, then our components are safe. Correct?

First of all I'm still wondering why the capacitors are in series: this reduces the capacitance and increases the total ESR. Higher ESR reduces the effectiveness absorbing the ESD pulse. I'd suggest placing these 47 nF parallel.

Next, like Analogsystemerf is already pointing out: layout matters. If these capacitors are far way from the point where the ESD pulse is applied or when the return current path is too long, trace inductance/resistance may make them useless absorbing the ESD charge: the charge may find a less impedance path, destroying components on its way.

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  • \$\begingroup\$ Thank you for the answer \$\endgroup\$ – Newbie Apr 28 at 6:55
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just because a component "breaks down" does not mean the component is destroyed.

ESD circuits are LAYOUT and SILICON_CONTACT critical ---- there is far more going on in an ESD event than what the schematic tells you.

The critical action is to steer the charge DEEP DOWN, so the heat goes DEEP into a big volume of silicon that absorbs the energy. Thus LAYOUT --- and metal widths and the number of contacts/well_ties/active_ties/etc all matter.

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What is DEEP DOWN?

Modern processes (low voltage) operate in the top 1 micron. So there is little silicon volume to absorb heat.

Yet the EPI (if you have that process methodology) is 10? microns deep, so why not craft the metal_active contacts with spacings to "encourage" the ESD transients to mostly use the deeper (1u to 10u) paths to transport the ESD charge??? That mindset, with intentionally_spaced contacts, is part of the ESD design degree_of_freedom.

Given the Bond Pads may be 100 micron on center_center, you have lots of room to encourage the huge transients to "go deep" and heat up the bulk silicon, instead of remaining near the surface and melting the very thin active implants.

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  • \$\begingroup\$ How does the "volume of silicon" relate to "Thus layout ...matter"? \$\endgroup\$ – Huisman Apr 25 at 20:30
  • \$\begingroup\$ Moreover what means "deep down". Most PCB's are just 1.6 mm thick... or do you mean it in a chips design level? I wonder if OP is working on the level.. \$\endgroup\$ – Huisman Apr 25 at 20:32

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