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I'm creating a 4-layer PCB design that takes a \$12\,\text{V}\$ DC input and converts it into 9 different voltages for various components on the PCB. I understand that a common stackup for 4-layer boards is signal, ground, power, signal. But, given the number of different voltages I have I'm not really sure how to break up my power plane. I could create a localized power plane for each component/set of components taking the same voltage, but this will make routing traces on the back side difficult since I will have to ensure the return current has an unimpeded path. I can do this by avoiding splits in the power plane or by placing a capacitor between the planes along the return current path. With the number of power plane splits I have this will be tricky and easy for me to make a mistake somewhere.

Instead, I'm considering allocating the 3rd layer almost entirely to a 2nd ground plane. This would make ensuring return current paths trivial. To satisfy the power rails, I'm planning to create very small, localized planes for each component. Basically just enough so that the IC power pins and bypass caps can connect to the power rails directly with a via. I would then connect this small plane to a power rail on the back side of the PCB with a ferrite bead. The power rails will then be routed as traces on the back side. This also makes it easy to have signals cross between the front and back layers since all the return current needs is a ground via adjacent to the signal via.

Does this seem like a decent solution to my problem? Are there any better ones? I took a look in Electromagnetic Compatibility Engineering by Ott and in section 16.4.2.2 he mentions this as a fairly effective stackup, which gives me some confidence in it.

As far as I can tell, the main downside to this approach is that I don't get distributed power supply bypassing between PCB layers. However, my 2nd and 3rd layers are much closer to the 1st and 4th layers respectively than to one another so the capacitance between layers should be negligible compared to the lumped capacitance from bypass caps. Any other major downsides?

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  • \$\begingroup\$ Return current paths might become trivial, but what about your power paths? Next to ground, power is the next highest thing to run everywhere and without a plane the power will be jumping and above and below traces everywhere. \$\endgroup\$ – DKNguyen Apr 25 at 23:55
  • \$\begingroup\$ I don't really see that as a problem. The power rails will just be like normal (albeit slightly wider) traces. Then I only need to connect 1 power trace to each mini plane. That's usually just 1 connection per IC, sometimes 2 or 3. Either way, its much less than the number of signal lines I have for each IC. Additionally, the current return paths for the power lines will also be taken care of by the ground plane. I really just have a little more than 10 power lines travelling across my board from the power supply. I'm using an FPGA so I have a lot more signal lines than that. \$\endgroup\$ – MattHusz Apr 26 at 0:44
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    \$\begingroup\$ If your planes are that small then yeah. Make sure to read Ott's article about changing reference planes since you wil be doing that with two ground planes. \$\endgroup\$ – DKNguyen Apr 26 at 0:51
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Something I've found very successful is to provide the currents from a bypass capacitor RIGHT AT THE POINT OF CONSUMPTION, and insert a SERIES RESISTOR of ONE OHM that comes from the regulator.

Thus the VDD current surges have a Local Battery (bypass capacitor) to provide the fast surges, and some series impedance (lossy ferrite bead or lossy resistor.

I like the resistors in series, because the LOSSES are guaranteed to exist at all frequencies, unlike the poorly defined behaviors of a bead.

Additionally, for when you need really-clean-power, the resistor+Capacitor is a well-defined Low Pass Filter that helps with Switch Reg trash that crept thru that LDO which at high frequencies has ZERO ability to adjust its servo-regulator-loop to reduce the trash.

A 1 ohm resistor and 100uF cap have 100uS time constant and a F3dB of 1,600 Hertz. Thus at 1,600,000 Hertz (typical switchReg trash/ringing frequency) you get up to 60 dB attenuation (the capacitor ESR and ESL, and PCB trace resistance set the ultimate floor).

And that resistor DAMPENS. Well damped filtering is a fine fine thing.

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