I am implementing a minimal I²C master, trying to keep it as simple as possible (but as complex as necessary). This master is a hardware peripheral - you could consider it part of an FPGA design, controlled by software.
The initial requirement for this project is that it supports multiple slaves but not multiple masters on the bus, so I'm wondering whether I need to implement the ability to generate "repeated start" conditions. As far as I understand those are only required retain control of the bus in the context of a multi-master setup; this is explained rather well on i2c-bus.org.
Are you aware of any slaves that strictly require the use of repeated starts? The I²C page on Wikipedia gives an example of a 24C32 EEPROM which uses repeated starts for random access reads, same is said in the part's data sheet. But neither sources mention whether it would also work with separate WRITE and READ transactions where each transaction is terminated by a STOP condition.