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In particular, are 5G oscillators found in cellphones using some kind of SMT/fabricated Gunn diode or Impatt diode(on a chip)? The frequency bands(K band) are beyond the range of crystal oscillators. But what other kinds of technology is used to generate oscillators this high in frequency using solid state?

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    \$\begingroup\$ "The frequency bands(K band) are beyond the range of crystal oscillators." So are the 2-3GHz clocks which CPUs run from. Look for 'pll'. \$\endgroup\$ – Oldfart Apr 27 '20 at 7:05
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The frequency is indeed out of range of a crystal oscillator. But you don't need a crystal to generate your fundamental directly. In fact, all previous frequency bands used in 2G/3G/4G are also out of range of these crystals.

The trick is to use a PLL. Modern CMOS circuit technologies can product fundamental oscillators past 150 GHz* - making one that oscillates at 30-40 GHz is not that difficult. You then use some kind of divider/mixer/counter to compare it with the crystal or MEMS oscillator that might be at 100 MHz or lower, and use the result to tweak the oscillating frequency of your high-frequency oscillator. The added advantage of this is that by tweaking the divider ratio, you can change the frequency of the high-frequency oscillator (for example to switch to a different channel), without needing a different reference.

*That was with planar CMOS, don't know how finfet performs since it's Ft/Fmax is generally lower than planar/FD-SOI

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  • \$\begingroup\$ Ahhhh, so you're using frequency multiplication. \$\endgroup\$ – Mr X Apr 27 '20 at 21:10
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    \$\begingroup\$ @MrX Frequency multiplication and PLLs are everywhere, especially in anything with a digital circuit. For exmaple, a 3.8 GHz CPU clock is generated by, for example, a 100 MHz external oscillator and a 38x "clock multiplier", which is performed by the PLL circuit on-chip. \$\endgroup\$ – 比尔盖子 Apr 28 '20 at 0:00
  • \$\begingroup\$ @比尔盖子 yes I'm aware. \$\endgroup\$ – Mr X Apr 28 '20 at 19:08
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The major technology step in high frequency oscillator sources is the need to BURN POWER in the Phase Lock Loop, so as to achieve a low Time Jitter.

I've seen people exult in their high speed processes, but in stumbling around with no design theory they produce Synthesizers that are 10 or 20 dB too noisy.

TimeJitter = CircuitNoise / SlewRate

and this simple formula needs to be applied at EVERY NODE that touches the edges.

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regarding the meaning of "step": I worked at a company dependent on, among other skills, being able to develop predictable noise-floor systems-on-chip, including amplitude noise and phasenoise and timing jitter.

Our advanced technology groups were just punting and hoping, producing some of the industry's most noisy circuits, and losing market share. They had no theories, because people tend to not straddle both systems and circuits; each can be a fine career in itself.

As I slowly worked thru concepts (where did the energy go?) to end up with the 3_variable equation I showed, I realized I needed to manage the SlewRate and the NoiseFloor (or NoiseDensity) and not be picky about saving a milliWatt of power.

Yet people using advanced processes (one of our divisions) will squeeze out all the power they can, while developing divide_by_32/33 Prescalars with horrid timing jitter. They cannot ignore the theory.

Turns out there is an ugly 4rth power cliff in FET application, when jitter is key.

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  • \$\begingroup\$ When you say "step" do you mean advancement that has already been made or hurdle to overcome? \$\endgroup\$ – DKNguyen Apr 27 '20 at 15:09
  • \$\begingroup\$ Oh, so you're saying that instead of focusing so much on low power, there needs to be more focus put into achieving low jitter at the expense of power? \$\endgroup\$ – DKNguyen Apr 27 '20 at 21:41

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