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I found the following question on a different site:

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______ .

Note – This question was Numerical Type.
(A) 14
(B) 15
(C) 16
(D) 12

The author claims the correct answer is 14. I do not understand why. Here is my reasoning. For an I-type instruction, we have 6 bits for the register and 4 bits for the immediate value. That leaves 6 bits left over for the opcode. That means that we should have 2^6 = 64 opcodes which means we have 64 - 8 = 56 R-type opcodes.

Another way to look at this problem is to say that an R-type instruction needs 12 bits for two register specifications. This leaves 4 bits for the opcode. Hence, there are 16 R-type opcodes. I am not sure about what happens because some of the I-opcodes overlap.

Hence, I am not sure what the right answer is, or how to get it?

Updated Answer:

Now for an R-type Opcode, I see
1-bit for a flag to specify if it is I or R format 12-bits to specify two registers
3-bits for the opcode

Now, I am seeing 8 different R opcodes because 2^3 = 8.

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Yes, 14 is right.

You have 8 I type codes, so you can have all I opcodes fit into 13 bits only.

That leaves 3 bits to determine if the opcode is I code or not. You can select one of the 8 bit patterns to indicate that the opcode is I code, which leaves 7 bit patterns for the R codes.

Since R code only needs 12 bits, you have one more bit to determine the R code, which doubles the 7 codes above to 14.

In other words, if 4 top bits define 16 codes, two of those must be reserved for I codes and 14 left for R codes.

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  • \$\begingroup\$ I do not understand this: You have 8 I type codes, so you can have all I opcodes fit into 13 bits only. Did you mean 3 bits? Also, could you comment on my updated answer where I get 8. \$\endgroup\$ – Bob Apr 27 '20 at 14:09
  • \$\begingroup\$ @Bob 6 bits to identify each 64 bit register + 4 for data + 3 to represent eight opcodes = 13 bits consumed for I-instructions out of a total of 16 bits in the instruction. \$\endgroup\$ – DKNguyen Apr 27 '20 at 14:12
  • \$\begingroup\$ I opcode: 4 bits immediate data, 6 bits register, 3 bits for which I opcode it is. 13 bits needed to decode I opcodes. 16-13=3 bits, or 8 codes, left for separating between I and R opcodes. One code reserved for stating it is an I instruction. It would leave 7 other codes for other 13-bit instructions, but since R opcodes are only 12-bit, you have 14 codes for R instructions. \$\endgroup\$ – Justme Apr 27 '20 at 14:21
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An alternative way of looking at it is that given 2 register addresses (12 bits) there are 4 bits left over, to (potentially) encode 16 R instructions leaving no space for I instructions. We'll call this 4-bit field the R instruction specifier.

Now consider what happens if we reserve one of those 4-bit R instruction codes for a set of I instructions? We have

  • 4 bit R instruction specifier
  • 4 bit immediate
  • 6 bit register address
  • 2 bits spare.

Therefore this R instruction specifier can encode 4 of our 8 I instructions using that 2 bit field. (We can call it the I instruction specifier)

The conclusion follows.

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