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I read this question, but it didn't really answer my question. I also want to preface this question by saying that I'm asking this from the perspective of being a computer science student that took one electrical engineering course.

In my notes on static RAM and dynamic RAM, it says that a single cell of static RAM is built entirely out of transistors, and will hold 1 bit of data as long as power is applied to the cell.

On the other hand, one cell of dynamic RAM is built primarily with a capacitor. I understand intuitively that a capacitor 'leaks' charge until the voltage on either plate is equal, and it says in my notes that this means that dynamic RAM must be refreshed every 10-100 milliseconds.

My question is why the refresh is necessary. What is the difference between power being applied to static RAM and dynamic RAM? Can't power be applied to dynamic RAM the same way as it does for static RAM to maintain the data? Why does it require a specific refresh signal?

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    \$\begingroup\$ "I understand intuitively that a capacitor 'leaks' charge until the voltage on either plate is equal" This isn't enough for you to understand why refresh is necessary? \$\endgroup\$
    – DKNguyen
    Apr 27 '20 at 18:24
  • \$\begingroup\$ But why isn't the power signal alone enough to keep it charged? Why is a separate refresh necessary? \$\endgroup\$ Apr 27 '20 at 18:25
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    \$\begingroup\$ Because the DRAM capacitor is not tied to power when holding a HI bit. Tying it to the power rail would require more transistors and adding them turns a DRAM cell into an SRAM cell. Remember, a DRAM cell is just one transistor. It can't do very much. \$\endgroup\$
    – DKNguyen
    Apr 27 '20 at 18:25
  • \$\begingroup\$ Ahhh, okay! That makes sense, thanks. \$\endgroup\$ Apr 27 '20 at 18:27
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    \$\begingroup\$ Look up the transistor configuration for a DRAM and SRAM cell. It should be fairly clear why if you understand what is going on at all in the schematic. \$\endgroup\$
    – DKNguyen
    Apr 27 '20 at 18:27
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Why refresh?

DRAM uses capacitors as storage cells. These capacitors, being really small and made from silicon, will leak off their voltage over time. That’s the D in DRAM: the cells are dynamic: their charge state changes.

To preserve the logic state of those leaky DRAM cells, their state must be read before their charge has bled off, then written back to bring their state to full, freshly-written charge. That’s refresh, in a nutshell.

To help deal with this, DRAMs implement a special kind of read-then-write cycle, called refresh, that hits multiple cells at once and writes them back. Typically, this is one or more rows of cells, about 1/256th of the DRAM at a time.

The host refresh operation is a race against time: all the DRAM rows have to be hit in time before their contents leak away. This usually works out to between 8 and 16ms to hit all the rows.

In contrast, Static RAM, or SRAM, uses a latch as a storage element. The latch keeps its state as long as the power is kept on or it’s written with a new value.

What does this mean with power and density?

SRAM can, in theory, have almost no standby power, as it uses a CMOS latch to store data. In practice, fast SRAM will have fairly high standby leakage current and even higher current during activity due to the use of low-threshold transistors to increase speed.

SRAM latches take between 4 and 8 transistors per bit, and all of them can leak.

More here: https://en.wikichip.org/wiki/static_random-access_memory

Meanwhile, DRAM has standby power to deal with refreshes. There’s considerable effort by chipmakers to offer low-power self-refresh modes that both stretches out the time between each refresh operation, and doesn’t require host intervention once that mode is entered. This self-refresh mode gets used in computer ‘sleep’ state, allowing CPU power-down yet enabling near-instant wake up time.

Density-wise, DRAM basically uses one transistor per cell, connecting to the capacitor which is dug vertically as a well into the silicon. This makes DRAM area per bit very small compared to the SRAM 6T or 8T latch cell. With fewer transistors, DRAM standby leakage per bit is also reduced.

More here: http://www.cse.scu.edu/~tschwarz/coen180/LN/DRAM.html#CellDesign

So overall, owing to its density and lower transistor count per bit, DRAM is substantially better power than fast SRAM; but substantially worse than slow, low-leakage SRAM because it requires refreshing.

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The critical point is that DRAM must be read to be refreshed correctly. You must read the capacitor voltage, then decide whether to refresh the value as a 0 or as a 1.

But there is no 'continuous read circuit' built into high-density dynamic ram chips. You have to address the RAM cell to read it and refresh it.

In contrast, you just apply a steady voltage to a static ram cell. A steady voltage maintains it in either it's 1 or 0 state.

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