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I am designing a USB-hub that has many USB traces. I followed some guidelines online and read forums. Based on my understanding of a 4-layer stack-up, one of the best set-up I chose is 8 mil trace space and 10 mil trace thickness. I made the layer under the Top Layer as the ground plan. Is it ideal?

My main question is: Should/could I have polygon pour on the top layer (the same layer is differential pairs)? I searched a lot and did not find any note about the impact of polygon on the impedance.

This image is an example of a connection: enter image description here

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  • \$\begingroup\$ How long are your traces? What speed USB? I assume D21 is a TVS? \$\endgroup\$ – Ron Beyer Apr 27 '20 at 22:15
  • \$\begingroup\$ that looks good for differential impedance. I don't know if the pour would affect the differential impedance. \$\endgroup\$ – Carl Gilbert Apr 27 '20 at 23:26
  • \$\begingroup\$ @RonBeyer They are pretty long, from 4 cm to even 25 cm. The MCU is at maximum Full Speed (12 MHz) and the HUB controller is a FE2.1. Yes, the D21 is a TVS diode, D1213. \$\endgroup\$ – amir_sh Apr 27 '20 at 23:54
  • \$\begingroup\$ Make sure you are doing length matching as well as impedence, at that distance you'll have to be very careful. Also, what is the text that is overlapping the mounting hole? C-something... \$\endgroup\$ – Ron Beyer Apr 28 '20 at 1:24
  • \$\begingroup\$ @RonBeyer I kept the difference in length less than 20 mils. And as you saw, I have 10 mil traces with 8 mil gap between. Based on the stack layer spec of the manufacturer, I see it should be 90 Ohm. Do you think everything is well maintained? (Other than taking the risk of lengthy traces). The text is just the bottom silkscreen. \$\endgroup\$ – amir_sh Apr 28 '20 at 3:50
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The pour is fine but it is too close to the traces and it ruins your impedance to be far lower. Same as if the PCB were too thin and the ground plane were too close. There is a 3W rule of thumb that says in your case that a diff pair with 10mil track width should have 30mil spacing to any track or plane. And the ESD diode should be in-line between connector and chip to protect the chip, not on a stub. Oh the stub is bad too.

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  • \$\begingroup\$ Thanks for the reply. I read a little about the 3W rule. It seems to be more about the crosstalk between two signals. Do you believe it is also true for my case which there is only GND around the differential pairs? About the ESD protector, if I put it in-line, then I have to put the diode on the back layer and use via. Isn't worst than what I had? \$\endgroup\$ – amir_sh Apr 29 '20 at 0:52
  • \$\begingroup\$ So, USB needs 90 ohms differential and 45 ohms single ended impedance. If you concentrate on only one wire, and have just determined the correct geometry you need to be 45 ohms without the pour, and then you put copper pour close to it, don't you think it changes the geometry and thus the impedance? About the ESD protector, I don't know which is worse, behind via or behind a stub. I just pointed out it's placement is not optimal. At least vias would get rid of the stub. \$\endgroup\$ – Justme Apr 29 '20 at 6:14
  • \$\begingroup\$ Yes, you are right. I know it makes sense to have impacts on the traces and impedances. But one thing that made me surprise and even hard to accept its impact was the less attention to polygon pour around differential pairs. I searched a studied a lot about how to calculate impedance of diff lines. But non of them talked about what if you add polygon pour, like EEWeblink or other tools. Maybe my search wasn't correct. So, what I did, made the polygon 30mils away from my diff pairs. I hope there shouldn't by any issue. \$\endgroup\$ – amir_sh Apr 29 '20 at 19:23
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find any note about the impact of polygon on the impedance.

Yes, copper poor around your differential stripline will substantially affect the characteristic impedance. With copper on the sides, this is called "dual co-planar waveguide"

enter image description here

You will need to find proper calculator for this strip configuration, and make proper corrections to you trace width and separations.

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I understand each track can be 45 Ohms so differential is 90 Ohms.

A coplanar differential raises the diff impedance while lowering Zo with adjacent grounds so it needs a thinner height of dielectric. (5mil prepreg)

enter image description here

But in your case if using a 10 mil dielectric;

enter image description here Impedance is almost constant ratiometric to the conductor geometry ratios if <2:1 ratios for planar and < 3:1 for differential coplanar. Planar includes top layer ground pour to differential coplanar, so you can get lower impedances with a smaller gap or dielectric height or wider track.

No pour around Tracks

For Width:Space:Height
Your design if using W:S:H= 10.0:8:8 mil, Zo = 55.2 Ohms, Z diff = 90.1 Ohms
Other design if used W:S:H= 9.4:16:6 mil, Zo = 46.7 Ohms, Z diff = 90.0 Ohms

with microvias between layers spaced apart.

The only advantage I see to copper pour around traces is less coplanar crosstalk if nearby.

YET a 2 layer board is possible but harder!

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