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I am using the pin planner of Quartus II to place my I/O signals on my Cyclone IV pins. I am stuck on the following fitter error:

Error (169029): Pin adc0_in[0] is incompatible with I/O bank 3. Pin uses I/O standard LVDS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 3.3V.

The Cyclone IV is organised in banks that should have the same VCCIO. The strange thing about this error message is that the pin adc0_in[0] has been placed on bank 8, not bank 3, so there should not be any contention. (Figure 6-10 from the datasheet shows that bank 8 and bank 3 use VCCIO8 and VCCIO3 respectively.)

I am also getting the error

Error (171169): Previous compilation results are reused as part of this compilation and may cause the error on this compilation.

but I have made sure that incremental compilation is not enabled (as suggested here) and that the database folders have been deleted (as suggested here).

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It turned out to be that the configuration device (a Max II) had pins on both bank 3 and bank 8, and was implicitly enforcing the restriction that bank 3 and bank 8 must have the same VCCIO. This was fixed by going to

Settings > Device > Device and Pin Options... > Configuration > Configuration device

and unchecking the box "Force VCCIO to be compatible with configuration I/O voltage".

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