I am using the pin planner of Quartus II to place my I/O signals on my Cyclone IV pins. I am stuck on the following fitter error:
Error (169029): Pin adc0_in is incompatible with I/O bank 3. Pin uses I/O standard LVDS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 3.3V.
The Cyclone IV is organised in banks that should have the same VCCIO. The strange thing about this error message is that the pin
adc0_in has been placed on bank 8, not bank 3, so there should not be any contention. (Figure 6-10 from the datasheet shows that bank 8 and bank 3 use
I am also getting the error
Error (171169): Previous compilation results are reused as part of this compilation and may cause the error on this compilation.