# What is the expected output of an LVDS IO cell of an FPGA (or just simulation) when the P and N pad inputs are both the same logical value?

I am curious what, in general, the output would be of an LVDS signal when both inputs are the same voltage level.

So if the truth table is:

P  N | Y
0  0 | ?
0  1 | 0
1  0 | 1
1  1 | ?


What would be 00 or 11 in terms of logic output? My assumption would be X (undefined) in sim and either no change or 0 in the real-world depending on the chip.

The reason I ask is because there is a tool I am using (logic equivalence checking which randomizes inputs and flags this as an issue in LEC). However, this a case I would not worry about because its LVDS and I would expect the chip to operate normally when powered on. Also, the issue occurs in RTL and not the gate-level output from PNR, so it seems to me the issue would not propagate X's throughout the system. I may be able to disposition this or dig into the tool's options to constrain the LVDS inputs as differential to perhaps skip this case.

They would be undefined, even in the real world. There needs to be enough voltage difference between them to reflect a proper ‘1’ or ‘0’ at the output of the differential receiver.

There wouldn't be much point to LVDS if it didn't use some decent level of hysteresis to avoid noise. Consider this picture from Maxim and regard the "Datastream" trace to be decoded from the LVDS shown signal below it: -

And now consider this modified picture: -

So, $$\\color{blue}{\text{what happens here}}\$$ to the received data i.e. what should a sensible receiver do at this point due to the glitch that makes "N" into a logical 0 from a logical "1".

The only sensible course of action is to not change state, just as it wouldn't change state here: -

In general, as with all components, you should study the datasheet for the specific component you're using.

Some LVDS receivers guarantee a particular output state when both inputs are exactly the same voltage, but most don't.

If you need to make an assumption, or run a simulation, then you should assume the output is undefined.