I am curious what, in general, the output would be of an LVDS signal when both inputs are the same voltage level.
So if the truth table is:
P N | Y 0 0 | ? 0 1 | 0 1 0 | 1 1 1 | ?
What would be 00 or 11 in terms of logic output? My assumption would be X (undefined) in sim and either no change or 0 in the real-world depending on the chip.
The reason I ask is because there is a tool I am using (logic equivalence checking which randomizes inputs and flags this as an issue in LEC). However, this a case I would not worry about because its LVDS and I would expect the chip to operate normally when powered on. Also, the issue occurs in RTL and not the gate-level output from PNR, so it seems to me the issue would not propagate X's throughout the system. I may be able to disposition this or dig into the tool's options to constrain the LVDS inputs as differential to perhaps skip this case.