I have bought this FPGA development board, which requires this tool to flash it. I have written some verilog to blink an LED, built it, flashed it onto the board, and I am waiting for the LED to flash.
Here's the contents of blinky.v:
module top( //top module CLK_i, LED0_o, LED1_o ); input CLK_i; //input 12Mhz clock output LED0_o; //output signal to LEDs output LED1_o; reg [24:0] counter; assign LED0_o = counter; assign LED1_o = counter; always @ (posedge CLK_i) begin counter <= counter + 1; end endmodule
Here's the contents of ice40hx8k.pcf:
### Clock set_io --warn-no-port CLK_i P7 ### LEDs set_io --warn-no-port LED0_o A5 # green LED set_io --warn-no-port LED1_o M4 # red LED
Here is my Makefile:
%.blif: %.v yosys -p "synth_ice40 -top top -blif $@" $< | tee logs/yosys.log %.asc: %.blif arachne-pnr -d 8k -p ice40hx8k.pcf $< -o $@ | tee logs/arachne-pnr.log %.bin: %.asc ice40hx8k.pcf icepack $< $@ | tee logs/icepack.log .PHONY: build build: blinky.bin .PHONY: flash flash: build iceFUNprog -P /dev/ttyACM0 blinky.bin .PHONY: clean clean: rm -rf blinky.asc blinky.blif blinky.bin
As you can see, you can build the binary with
make and program the board with
I am certain that the correct module is "top", (I'm new to verilog but so far as I can tell, "top" is analogous to what "main" is in C). I am certain that the binary is reaching the FPGA; the
iceFUNprog program writes the binary and verifies it okay. I've looked up the pins for the two LEDs and the clock input in the datasheet, and these details are in the file
I'd expect to see some pulse @ 3 MHz (that's bit 3 of the counter) and another much slower pulse, which is bit 24 from the counter. If I've calculated correctly, that's 500kHz. Since I don't see anything on the LEDs, I've gotten an oscilloscope out to try to find these pulses. I've found a 12MHz pulse on one of the pins of the microcontroller (this is presumably the same clock which is fed to the FPGA). But I don't see any other movement. The LEDs are constantly off, and the pins on the two connectors are all either constantly high or constantly low.
Is there an error in my verilog somewhere? Or what am I doing wrong?