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I have bought this FPGA development board, which requires this tool to flash it. I have written some verilog to blink an LED, built it, flashed it onto the board, and I am waiting for the LED to flash.

Here's the contents of blinky.v:

module top( //top module
    CLK_i,
    LED0_o,
    LED1_o
);

input CLK_i;    //input 12Mhz clock
output LED0_o;  //output signal to LEDs
output LED1_o;

reg [24:0] counter;

assign LED0_o = counter[24];
assign LED1_o = counter[3];

always @ (posedge CLK_i) begin
    counter <= counter + 1;
end

endmodule

Here's the contents of ice40hx8k.pcf:

### Clock
set_io --warn-no-port CLK_i P7

### LEDs
set_io --warn-no-port LED0_o A5 # green LED
set_io --warn-no-port LED1_o M4 # red LED

Here is my Makefile:


%.blif: %.v
    yosys -p "synth_ice40 -top top -blif $@" $< | tee logs/yosys.log

%.asc: %.blif
    arachne-pnr -d 8k -p ice40hx8k.pcf $< -o $@ | tee logs/arachne-pnr.log

%.bin: %.asc ice40hx8k.pcf
    icepack $< $@ | tee logs/icepack.log

.PHONY: build
build: blinky.bin

.PHONY: flash
flash: build
    iceFUNprog -P /dev/ttyACM0 blinky.bin

.PHONY: clean
clean:
    rm -rf blinky.asc blinky.blif blinky.bin

As you can see, you can build the binary with make and program the board with make flash.

I am certain that the correct module is "top", (I'm new to verilog but so far as I can tell, "top" is analogous to what "main" is in C). I am certain that the binary is reaching the FPGA; the iceFUNprog program writes the binary and verifies it okay. I've looked up the pins for the two LEDs and the clock input in the datasheet, and these details are in the file ice40hx8k.pcf.

I'd expect to see some pulse @ 3 MHz (that's bit 3 of the counter) and another much slower pulse, which is bit 24 from the counter. If I've calculated correctly, that's 500kHz. Since I don't see anything on the LEDs, I've gotten an oscilloscope out to try to find these pulses. I've found a 12MHz pulse on one of the pins of the microcontroller (this is presumably the same clock which is fed to the FPGA). But I don't see any other movement. The LEDs are constantly off, and the pins on the two connectors are all either constantly high or constantly low.

Is there an error in my verilog somewhere? Or what am I doing wrong?

Related meta question

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    \$\begingroup\$ "Is there an error in my verilog somewhere?" You didn't post that, or a diagram of how you hooked it up, so how can we know? \$\endgroup\$ – Ron Beyer Apr 29 '20 at 13:52
  • \$\begingroup\$ @RonBeyer, my post contains a link to the verilog I wrote. \$\endgroup\$ – OmarL Apr 29 '20 at 13:58
  • \$\begingroup\$ @RonBeyer Like this? I hope it's better now \$\endgroup\$ – OmarL Apr 29 '20 at 15:30
  • \$\begingroup\$ I like this because I have had an iCE40 devboard staring at me for months and I also have to learn how to write a blinky one day. \$\endgroup\$ – pipe Apr 30 '20 at 19:57
  • \$\begingroup\$ Make your code just set the pins HI. And then another version that makes it just set them LO. Do they both work? If it doesn't then your pin configuration is wrong. \$\endgroup\$ – DKNguyen May 4 '20 at 19:31
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EDIT: I checked https://www.robot-electronics.co.uk/files/iceWerx.pdf, I believe A5 and M4 are NOT the names of FPGA's pins - look for the pin names on the banks - those look to be P208 and P63.

If the input clock is indeed 12MHz, then counter[3] would be 1/2^3=1/8 of that (1.5MHz) - how do you expect to see that with a naked eye?

counter[24], OTOH, should be 1/2^24 of 12MHz, which is roughly 0.7Hz - you definitely should see that!

Some tools are very aggressive with optimization - check documentation if it's possible to inspect intermediate artifacts, like RTL netlists.

Are there any demo designs for the board? Do they work on your board? If not, then it's broken. If yes, use them as a starting point, cutting off pieces iteratively and checking if the remaining functionality still works.

As other suggested, you can also start with an even simpler design - just write constant 1 to one LED and constant 0 to the other.

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