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I want to check my understanding which I have gleaned from several sources, many of which seem to be out of date and many of which are conflicting.

My understanding is that there is just ONE CLOCK inside a modern PC that regulates pretty much everything. It is an oscillator that depends on the vibration of a quartz crystal and it outputs a frequency of 100 MHz and a frequency of 133 MHz. This clock/oscillator is located in a chip on the motherboard (the 'chipset'), NOT INSIDE THE CPU as some literature seems to suggest. There are however multiplier circuits INSIDE THE CPU which can increase the 100 MHz signal (about 35 times to 3.4 GHz) in order to to control program execution. The 133 MHz signal is supplied by the same clock to the memory controller and is multiplied up (about 16 times) to regulate the speed of the memory bus. The memory controller is also inside the CPU. There is no front side bus any more.

Could you please let me know if this information is correct, in particular, the location the clock and that there is only one clock?

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    \$\begingroup\$ It would be up to the computer and what else it had. If you take a look at a standard PC motherboard, you will see plenty of crystals. \$\endgroup\$
    – Justme
    Apr 29, 2020 at 15:24
  • \$\begingroup\$ In PC there are PLL oscillators (phase locked loop) and you are right there is usually only 1 clock generator chip on the motherboard and CPU does the multiplying \$\endgroup\$
    – Healow
    Apr 29, 2020 at 15:27
  • \$\begingroup\$ What do you mean by "personal computer"? Does it have a real-time clock? Does it have a dedicated graphics processor? \$\endgroup\$ Apr 29, 2020 at 15:30
  • \$\begingroup\$ Quick Google image search shows at least 2-3 crystal oscillators just on the visible parts of most PC boards. I think at least an extra 32khz one is used for the real time clock. If you're asking about just the CPU, you'd have to specify the model and then look at the engineering manuals to see what the input clocks required are. \$\endgroup\$ Apr 29, 2020 at 15:32
  • \$\begingroup\$ Ultimately, the number of clocks is driven by the need for different clock frequencies for peripherals and the required accuracy of those frequencies. If you could achieve it with one clock, you would. Otherwise add another crystal. No real definitive answer. \$\endgroup\$ Apr 29, 2020 at 15:46

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there are a great number of clocks and clock sources, no there isnt just one clock.

Yes the x86 is very likely driven by a reference clock with plls inside, that does not mean the insides only run on the one clock there are likely esp with the current ones MANY clocks inside derived off of that clock.

The pcie may have its own reference clock or it may generate one, these days the pcie root complex is part of the main processor package and not a separate chip.

Networking generally has its own reference clock so another oscillator plus plls inside. The wifi modules are purchased like seatbelts and airbags for a very short list of suppliers for those so they will have their own clock sources.

Your pc is dripping with microcontrollers and other similar embedded devices hidden inside other parts (networking phys, battery management, keyboard, mouse, etc, etc, etc). Most of these will have their own clocks and sometimes plls. Higher end microcontrollers can/will run off of more than one one for an rtc for example the main clock can be multiplied but the subsections of the chip will run off of divisions of that and if you have ethernet or other similar interface there is probably another oscillator for that, but it depends on the implementation.

As mentioned the RTC will have its own oscillator plus circuits ideally to keep everything stable temperature-wise or other so that the reference clock doesnt drift as much.

Now if you want to think text book not real world or some subset of the real world processor based products then yes you cant have all the large pins or balls at high speed without issues and you can make the insides go way faster than the outside and on and on, so the typical solution is a reference clock where 100mhz is not uncommon but there are others as well since oscillators are so expensive. Then internally you multiply that up to what the chip can run or your power or cooling can support, etc and ideally you run the chip off of divisions of that clock. No reason to run the uart logic at 4Ghz for example, that is just a waste of power, so you would design a peripheral bus internally that is clocked at a slower rate with a clock domain boundary, if simply a divisor of the main clock then much easier to deal with but sometimes you will have different plls. (Oh that reminds me the dram controller possibly uses the main clock but probably has its own plls, have seen designs with many of them).

And you evolve to what folks like intel use where certainly the power feeding the chip can be constantly adjusted to minimize consumption (yet another processor inside the chip running code to manage that independent of the x86) plus I would expect dynamic clock speed features as well which have been around in some form but likely keep getting better. but you cant for example mess with the usb clocks so you have to keep that fixed, dram you should keep fixed. pcie has specs, video, etc etc.

yes on a per isolated module basis it is not uncommon to have a reference clock and a pll inside and the internals run off the one clock or various divisions of the pll or of the main/fast clock.

PCs have MANY processors and MANY separate clocks some are crystal based and some are not. And there would need to be more than one crystal to support everything going on in there and no way possible to fan out one crystal to the whole box.

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  • \$\begingroup\$ Thank you for the detailed answer. I wonder how synchronous DRAM is synchronised. Is it correct to say that in a typical PC (if there is such as thing as typical) the CPU and the memory bus are regulated by the same oscillator? When I inspect my computer with CPU-Z, my core speed is a multiple of 100 MHz, but my DRAM frequency is a multiple of 133 MHz. If the CPU and DRAM are using different oscillators, surely there is a risk they will be out of phase by an unpredictable amount. Is 133 MHz derived from 100 MHz somehow or is it from a different oscillator? \$\endgroup\$
    – Drummy
    Apr 30, 2020 at 13:17
  • \$\begingroup\$ you can do it with the 100mhz, the products I work on do. we dont have a separate oscillator for the dram but we have many plls so we can get the frequency as it wont be a division of the vco from the main clocks pll. thats were the 1333.3333 1666.6666 and such come from there is a divide by three in there. \$\endgroup\$
    – old_timer
    Apr 30, 2020 at 14:37
  • \$\begingroup\$ yes you have clock domain crossings within or between these logic blocks that have to be well designed. same goes for pcie and network and others. even with the same reference clock separate plls will jitter independently (even if they are generating the "same" speed clock) so you have to define your clock domains and cross them safely. \$\endgroup\$
    – old_timer
    Apr 30, 2020 at 14:38
  • \$\begingroup\$ at this point I would think the term synchronised in sdram is misleading, perhaps someones marketing term from the beginning. clearly the processor and the dram are separate clock domains and there is a crossing, the processor has its busses the dram has its. you buy a dram controller which provides processor side interfaces, you ideally put a cache in front of it to make life easier for everyone but the validation and mfg test teams. the processor can do from byte sized transfers on up on its side of the \$\endgroup\$
    – old_timer
    Apr 30, 2020 at 14:45
  • \$\begingroup\$ cache, and on the dram controller side of the cache you can then make all the transfers cache line sized which would be an integer multiple of the dram bus size meaning no read-modify-writes on the dram side. Doesnt mean everyone does it this way but its a nice clean solution. and the dram side of the cache of course is in the processor clock domain and the dram controller essentially is sitting across both domains dram side and cache/processor side. \$\endgroup\$
    – old_timer
    Apr 30, 2020 at 14:47
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There's several clocks:

  • real-time clock (RTC) that is battery backed
  • system reference clock from which other clocks are defined
  • external (internet) clock

The RTC (sometimes called the 'CMOS', since it used to be part of the battery-backed RAM) is a small, low-powered timekeeping clock that runs on a low-frequency watch crystal. When the system is off, this clock is kept alive with a small battery such as a coin cell, or in some cases, a supercapacitor. This defines the wall-clock time when the system starts up, and also when there isn't a reliable external time reference available.

The system reference clock is a crystal or oscillator that feeds the motherboard chipset and CPU. Typically the crystal is tens of MHz; it can be multiplied up for distribution (details are chipset-dependent.) This clock in turn drives the various PLLs that define the processor, memory and I/O clocks. The CPU bases its time-tick on this clock when it's running, and will at certain times synchronize its computed wall-clock time to a known-good value from an external source.

Finally, computers connected to a network will get wall-clock time from a traceable source, often using a protocol called NTP, or Network Time Protocol. More about that here: http://www.ntp.org/

Neither the RTC or system reference clocks are especially accurate, having typical crystal frequency errors in the 10 ~ 50ppm range. NTP provides an authoritative, atomic-clock reference standard which is used not only to correct the drift on system time-tick clock, but also to update the RTC.

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  • \$\begingroup\$ This is beginning to make more sense. I am still a little confused though. When I inspect my own computer with CPU-Z, I can see that the CPU multiplies up 100 MHz about 35 times to give me a core speed of 3.5 GHz. The information I see about the RAM suggests a base clock rate of 133MHz. Is this new speed a result of multiplying 100MHz in some way? \$\endgroup\$
    – Drummy
    Apr 30, 2020 at 12:31
  • \$\begingroup\$ It depends on the clock PLL and how it can multiply up and down. PLLs can have dividers on the input, the feedback, or the output. If, for example, they used a reference of 100, pre-divided that by 3 to 33.33, then multiplied that up by 100 to 3.333 GHz, then they can have a PLL with steps of 33.33MHz. \$\endgroup\$ Apr 30, 2020 at 16:24
  • \$\begingroup\$ Got it. Thanks. \$\endgroup\$
    – Drummy
    Apr 30, 2020 at 16:31
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In a microcontroller, you're likely to have just one clock, and typically a bunch of PLLs to get derivative clocks. In a PC you're likely to have multiple clocks.

There will typically be:

  • The CPU clock you mentioned
  • A real-time clock (RTC), which runs constantly at low current while the machine is off

In addition, other peripherals may have their own clocks, particularly if their timing constraints differ from the CPU clock, if they're on add-on devices/cards, or if they need to run while the CPU clock is idle.

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  • \$\begingroup\$ In actuality almost all modern MCUs have multiple clocks/oscillators, especially any that offer a PLL will as they want to offer low power/low speed alternatives for where starting up that system is not desired, and because things like watchdogs should arguably not depend on it. Even if there's only a single clock routing there will be multiple oscillators which can be chosen to feed it - on chip low speed, on chip high speed, external crystal, etc. Only the oldest or most barebones parts have a single oscillator. \$\endgroup\$ Apr 29, 2020 at 16:25

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