there are a great number of clocks and clock sources, no there isnt just one clock.
Yes the x86 is very likely driven by a reference clock with plls inside, that does not mean the insides only run on the one clock there are likely esp with the current ones MANY clocks inside derived off of that clock.
The pcie may have its own reference clock or it may generate one, these days the pcie root complex is part of the main processor package and not a separate chip.
Networking generally has its own reference clock so another oscillator plus plls inside. The wifi modules are purchased like seatbelts and airbags for a very short list of suppliers for those so they will have their own clock sources.
Your pc is dripping with microcontrollers and other similar embedded devices hidden inside other parts (networking phys, battery management, keyboard, mouse, etc, etc, etc). Most of these will have their own clocks and sometimes plls. Higher end microcontrollers can/will run off of more than one one for an rtc for example the main clock can be multiplied but the subsections of the chip will run off of divisions of that and if you have ethernet or other similar interface there is probably another oscillator for that, but it depends on the implementation.
As mentioned the RTC will have its own oscillator plus circuits ideally to keep everything stable temperature-wise or other so that the reference clock doesnt drift as much.
Now if you want to think text book not real world or some subset of the real world processor based products then yes you cant have all the large pins or balls at high speed without issues and you can make the insides go way faster than the outside and on and on, so the typical solution is a reference clock where 100mhz is not uncommon but there are others as well since oscillators are so expensive. Then internally you multiply that up to what the chip can run or your power or cooling can support, etc and ideally you run the chip off of divisions of that clock. No reason to run the uart logic at 4Ghz for example, that is just a waste of power, so you would design a peripheral bus internally that is clocked at a slower rate with a clock domain boundary, if simply a divisor of the main clock then much easier to deal with but sometimes you will have different plls. (Oh that reminds me the dram controller possibly uses the main clock but probably has its own plls, have seen designs with many of them).
And you evolve to what folks like intel use where certainly the power feeding the chip can be constantly adjusted to minimize consumption (yet another processor inside the chip running code to manage that independent of the x86) plus I would expect dynamic clock speed features as well which have been around in some form but likely keep getting better. but you cant for example mess with the usb clocks so you have to keep that fixed, dram you should keep fixed. pcie has specs, video, etc etc.
yes on a per isolated module basis it is not uncommon to have a reference clock and a pll inside and the internals run off the one clock or various divisions of the pll or of the main/fast clock.
PCs have MANY processors and MANY separate clocks some are crystal based and some are not. And there would need to be more than one crystal to support everything going on in there and no way possible to fan out one crystal to the whole box.
