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I was reading the chapter about Op - Amp design in Microelectronic Circuits by Sedra Smith, and I have some questions about the so called "common mode feedback" (CMFB) which is used to control some current mirrors.

Let's consider this scheme:

enter image description here

The book says:

Relying solely on matching will not be sufficient to ensure that the currents supplied by Q9 and Q10 are exactly equal to the currents supplied by Q7 and Q8. Any small mismatch \$\Delta\$I between the two sets of currents will be multiplied by the large output resistance between each of the collector nodes and ground, and thus there will be large changes in the voltages vO1 and vO2. These changes in turn can cause one set of the current sources (i.e., Q7 −Q8 or Q9 −Q10) to saturate. We therefore need a circuit that detects the change in the dc or common-mode component VCM of vO1 and vO2, VCM = 1 2 (vO1 +vO2) and adjusts the bias voltage on the bases of Q7 and Q8, VB, to restore current equality. This negative-feedback loop should be insensitive to the differential signal components of vO1 and vO2; otherwise it would reduce the differential gain. Thus the feedback loop should provide common-mode feedback (CMF).

I have the following questions:

1) How is it possible that for instance current of Q9 is different from that of Q7? Their channels are in series (since the load is supposed to be of infinite impedance) and so, by kirchoff current law, all the current through Q9 should go on Q7, I think...

2) Does the book refer to DC or signal currents?

3) Why do we decide that the CMFB has to read the common mode voltage? Suppose there is a mismatch between current of Q9 and current of Q7: there would be a spurious value inside vO1. Which is the link between this spurious voltage, and the common mode voltage between the outputs in 1 and 2?

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1) The currents of Q7/Q8 and Q9/Q10 are set by the bias voltages. It is very difficult to get this bias voltage exactly right without a feedback network, so the theoretical collector currents would differ. This discrepancy in current results in wild shifts in output voltage as a result of the Early effect (i.e. R_out in the small-signal model of each BJT).

2) The DC bias itself is susceptible.

3) This portion of the question isn't that clear. We want to regulate the common-mode voltage because it is part of the desired specification of a differential amplifier: as the outputs swing up and down with a differential input, they swing around a well-regulated constant common-mode voltage. If we regulated Q7 and Q8 using only the voltage at vO1, we wouldn't get a fully differential amplifier; instead we would get something along the lines of a differential-to-single-ended amplifier.

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  • \$\begingroup\$ Regarding 1), so the current discrepancy will flow in the output resistance of Q7 or Q9? Regarding 3), I do not understand the connection between "common mode" and "current mismatch". Since the CMFB reads the common mode voltage, it seems to me that the problem is not the current mismatch itself and the transistor saturation, but the different current mismatches between right and left transistors (for instance 100uA of mismatch at right and 200uA of mismatch at left) \$\endgroup\$ – Kinka-Byo Apr 29 at 16:43
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    \$\begingroup\$ @Kinka-Byo Correct, the discrepancy flows through the output impedance of the BJT. For 3), the important mismatch is between upper and lower BJTs, since it will saturate both together, and can be severe. Left-right matching can be done with good layout, and contributes to an offset voltage rather than saturation of both outputs. When it's matched that well, the current mismatches can be on the order of 0.1 uA or less, rather than 100s os uA. Remember that when the amplifier has a non-zero differential input, we want a small current mismatch as it's how the amplifier actually works. \$\endgroup\$ – nanofarad Apr 29 at 16:48
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How is it possible that for instance current of Q9 is different from that of Q7? Their channels are in series (since the load is supposed to be of infinite impedance) and so, by kirchoff current law, all the current through Q9 should go on Q7, I think...

Assume that you have identical transistors including pnp and npn. Suppose you set the bias \$V_B\$ such that \$V_{BE_{pnp}} \ne V_{BE_{npn}}\$. Assuming the system starts with both the transistors in active region, the two transistors are going to have different currents. Let's say npn has smaller \$V_{BE}\$, thus at node \$v_{O1}\$ less current is being sunk to ground then what is being sourced from supply. The potential at this node will rise as a result. And in steady state or DC the pnp will go into saturation. In DC, the current through the pnp is same as npn but you will loose all the gain as pnp is saturated. This needs to be avoided via CMFB.

Does the book refer to DC or signal currents?

As explained, DC Currents.

This portion of the question isn't that clear. We want to regulate the common-mode voltage because it is part of the desired specification of a differential amplifier: as the outputs swing up and down with a differential input, they swing around a well-regulated constant common-mode voltage. If we regulated Q7 and Q8 using only the voltage at vO1, we wouldn't get a fully differential amplifier; instead we would get something along the lines of a differential-to-single-ended amplifier.

CMFB will regulate the DC level of both \$v_{O1}\$ and \$v_{O2}\$. In fact, common mode is always defined for a pair of signals. Thus CMFB would regulate \$v_{CM} = \frac{v_{O1}+v_{O2}}{2}\$.

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