Why is that the output signal is clipped despite the fact that the transistor's q point is located halfway of Vcc???

here is the schematicenter image description here

and clipping here

enter image description here From my analysis, as you can see, supply Vcc is around 40 volts and the multimeter reading of the collector voltage is around 20 volts (half of 40 so the q point / quiescent point is in the middle to avoid cut off and saturation)

enter image description here

Finally, you can also see that the output voltage swing is around 12 Volts rms (so that translates to 34 volts peak to peak, way far from the 40 volts of DC supply voltage)

Ref. http://www.mediafire.com/download.php?htnopk49oj1y9sj multisim


Don't forget that there is a quiescent (no-signal) DC voltage on the emitter bypass capacitor which should be roughly 6.7V if the quiescent DC voltage on the collector is roughly 20V.

The negative swing for AC signals is then roughly limited to the difference, 13.3V.

Since the positive swing should be 20V, this would give a maximum peak to peak of roughly 33.3V.

For this circuit, if you want roughly symmetric clipping, you'll want the quiescent collector voltage halfway between 40V and the quiescent emitter voltage.

  • \$\begingroup\$ In other words, if the signal is clipped at both cutoff and saturation, we must make the input signal smaller, so that the whole reproduction is symmetrical and no clipping. am i correct? \$\endgroup\$ – WantIt Nov 24 '12 at 2:23
  • \$\begingroup\$ one more thing, puu.sh/1tAAk how can we make the output signal centered in the x-axis?? i thought that would be the first thing to do(centering the output on the 0 level), and then minimize the input signal \$\endgroup\$ – WantIt Nov 24 '12 at 2:25
  • 1
    \$\begingroup\$ @vvavepacket, yes you must reduce the input signal to remove the clipping. But, keep in mind the points I'm making in my answer: (1) you can't approach 40Vpp unclipped and (2) you will get maximum unclipped Vpp when the amp clips symmetrically, i.e., the positive and negative peaks begin to clip for the same level of input signal. \$\endgroup\$ – Alfred Centauri Nov 24 '12 at 12:18

You've just discovered that the AC load line is different from the DC load line.

Although the amplifier swings about your DC load point, the disturbance does not follow the DC load line.

Generally speaking, the AC load line crosses the DC load line at the Q point, but is more steep, so it intercepts the horizontal axis at a smaller voltage than the DC load line.

To maximize the AC swing, you have to relocate the Q point.

The different slope is because AC sees different impedances. The impedance of the base-emitter junction of the transistor is different for AC. The impedance of the emitter branch is different (because of the bypass resistor). To AC, both the positive rail and ground look like a ground.

AC and DC load line video: http://www.youtube.com/watch?v=lMPPDpia2lc

  • \$\begingroup\$ best explanation so far \$\endgroup\$ – WantIt Nov 24 '12 at 2:47

As far as I can see, that poor little 2N3904 is dissipating about a watt under quiescent conditions, and rather more under signal. Isn't it getting rather hot?

  • \$\begingroup\$ Yea it does, what can u suggest to reduce heating and yet still amplify and produce same results \$\endgroup\$ – WantIt Nov 24 '12 at 11:46
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    \$\begingroup\$ The first thing I would do is double Rc to 600 ohms. Then re-adjust the bias chain to halve the voltage across Re, which will restore the quiescent collector point. By reducing the volts lost across Re, this will also recover some of your missing AC volts... Increasing Rc much further would diminish the ability to drive a 1k load. Then to avoid clipping you can do 2 things: (1) reduce input signal or better,(2) reduce gain. This is easy; put 22R in series with Ce and see what happens. (Vary it later) \$\endgroup\$ – Brian Drummond Nov 24 '12 at 12:18

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