On my prototype board I used an integrated oscillator which gave me the desired frequency without any extra component. Then it's being divided by a divider ic. The clock pulse going from the oscillator to the 8 stage divider 74AHC1G4208 is turned on and off by an AND gate. The ON-OFF signal comes from a D Flip-Flop CD4013. On the prototype I use a 10 stage divider. But in the final version I will use a 8 stage divider, which is the same. So I linked to the 8 stage version of the chip.
This circuit works perfectly. Now that I plan production in some quantity, I would like to replace the oscillator ic by a much cheaper and also more available, crystal and its passive components, as shown on this schematic from the divider ic 74AHC1G4210 datasheet. This chip has an built-in output X2 for oscillator circuit. X1 is the clock input being divided. I plan to copy this circuit.
The crystal is an IQD 4.9152 MHz.
Could you tell me how I can turn this circuit on and off as I did with the AND gate. If I put an AND gate between the crystal and X1, I imagine it won't work because the AND gate will prevent resonance with the crystal.
Maybe I could sink the current coming from X2 to the crystal, limited by R1 (in this case 4.7K or 10K) with a N-MOSFET? But wouldn't that perturb the crystal?
The first 5 or 6 pulses can be irregular, as long as the next ones are at the good frequency.
I also have no idea what value should be for Rbias, C1 and C2, except from the indication on this schematic. It reads: "R1 is the power limiting resistor, its value depends on the frequency and required stability against changes in VCC or average ICC. For starting and maintaining oscillation a minimum transconductance is necessary, so R1 should not be too large. A practical value for R1 is 2.2 kΩ."