I am trying to understand how DRAM burst mode is compatible with bank interleaving.
Once a row within a DRAM memory array has been activated, sensed and buffered, according to the strobed row address, adjacent bits within the same row can be accessed very quickly by varying the column address for the same row, without the overhead of pre-charging, sensing, etc. Indeed, the column address can be changed as fast as the clock supplying the data.
The first part of my first question is, do we refer to this as ‘burst mode’ and how does it differ from ‘fast page mode’ which I understand is now obsolete ?
If multiple arrays within the same BANK, let’s say 8 of them, are supplied the same row and column addresses (but a different line of the data bus), then it is possible to read or write 8 bits simultaneously in the same way (burst mode, fast page mode, or whatever it's called).
I also understand that data can be interleaved across multiple banks within a CHIP. For example, a read request, for a particular memory address, can be issued to a bank, but there is no need to wait for the data to be returned before issuing a read request to a different bank within the same chip. When I try to visualise what is going on inside the chip, I imagine 8 bits coming from one bank, then 8 from the next, and so on. (I also imagine there are 8 chips all doing the same thing to keep a 64 bit data bus busy.) Interleaving groups of 8 bits across multiple banks within the same chip does not seem to be compatible with burst mode which expects successive groups of 8 bits to be adjacent. My second question then, how do burst mode and bank interleaving work together, if at all?