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I am trying to understand how DRAM burst mode is compatible with bank interleaving.

Once a row within a DRAM memory array has been activated, sensed and buffered, according to the strobed row address, adjacent bits within the same row can be accessed very quickly by varying the column address for the same row, without the overhead of pre-charging, sensing, etc. Indeed, the column address can be changed as fast as the clock supplying the data.

The first part of my first question is, do we refer to this as ‘burst mode’ and how does it differ from ‘fast page mode’ which I understand is now obsolete ?

If multiple arrays within the same BANK, let’s say 8 of them, are supplied the same row and column addresses (but a different line of the data bus), then it is possible to read or write 8 bits simultaneously in the same way (burst mode, fast page mode, or whatever it's called).

I also understand that data can be interleaved across multiple banks within a CHIP. For example, a read request, for a particular memory address, can be issued to a bank, but there is no need to wait for the data to be returned before issuing a read request to a different bank within the same chip. When I try to visualise what is going on inside the chip, I imagine 8 bits coming from one bank, then 8 from the next, and so on. (I also imagine there are 8 chips all doing the same thing to keep a 64 bit data bus busy.) Interleaving groups of 8 bits across multiple banks within the same chip does not seem to be compatible with burst mode which expects successive groups of 8 bits to be adjacent. My second question then, how do burst mode and bank interleaving work together, if at all?

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    \$\begingroup\$ There have been many DRAM families with differing capabilities; which are you asking about? \$\endgroup\$ – Peter Smith May 2 '20 at 12:35
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First part: No, what you have described is in fact "fast page mode" and not burst mode. This mode only applies to old-fashioned non-synchronous DRAMs (and not all of them supported it), which don't have internal banks, and not to any kind of modern SDRAM.

Second part: Yes, it is possible to interleave burst accesses to multiple banks within an SDRAM chip, and in fact, this allows you to get close to 100% utilization of the data bus. All of the overhead of initiating an access to one bank can be hidden by the data transfers occurring on other banks. I do this all the time when building frame buffers for video processing.

Don't worry about the fact that the data is "non-adjacent" — that's just a matter of how you assign the address bits. There's nothing that requires data that the CPU thinks is "adjacent" in its address space to be physically adjacent in the memory chips. Think of it like striping in a RAID array — a block of 256 data words can be split up into four 64-word blocks, each one written to a different bank.

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  • There are DRAM chips of varying densities, and they can be combined to have larger densities and/or wider busses.
  • Banks are largely independant. It's like having several RAM chips in parallel.
  • Different generations of SDRAM/DDRAM have different constraints on accesses. While old SDRAM support simple accesses, latest generations are far better suited for bursts (due to access overheads).

SDRAM/DDRAM don't have very short latency, new generations offer more bandwidth but actual access times to random cells haven't been reduced that much these last 20 years. If you actually need to do fast random accesses (for example every 5ns) other RAM technologies such as QDR or RLDRAM can be better. Alternatively, some applications can tolerate variable access times and a cache can help reduce average latency.

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