I've made level shifting circuit to shift pulsed ~10 kHz 5 V signal to 15 V by using gate driver and level shifter IC: TC4427 and CD4504.

There is a condition that the circuit output should be 0 when "enable" bit is zero. I have done that by placing an optocoupler to disconnect main 15 V supply from the ICs, but only after assembling and testing I have found out that ICs have these ESD protection diodes from input to VCC which leads to condition that input has to be always < VCC + 0.3 V.

Now when enable is 0, the +15V VCC floats. Now when I connect input i get some voltage at the VCC rail and outputs of IC:s because the voltage is "leaking" through the esd protection diodes.

Is there any workaround that could be done with minimal changes to the design so that the output will be as close to zero as possible (while there is still pulsed 5V input)?

Of course by still keeping the lifetime expectancy of ICs as high as possible. Condition where enable is 0 while there is some input voltage is quite rare and not normal operating condition.


  • \$\begingroup\$ Welcome to EE. What VCC do you mean (\$+15V, +5V, +15V_{ne}\$)? \$\endgroup\$ – vtolentino May 3 at 8:37
  • \$\begingroup\$ "There is a condition that the circuit should not work when "enable" bit is zero." - By 'not work' you mean the outputs should stay low, right? What is the maximum acceptable propagation delay and transition time? \$\endgroup\$ – Bruce Abbott May 3 at 8:50
  • \$\begingroup\$ Hi, thanks for reply! I think I mean +15V and +5V. +15Vne is supposed to be a rail not affected by enable bit. \$\endgroup\$ – Jesse Haataja May 3 at 8:51
  • \$\begingroup\$ By 'not work' I meant that the output should stay low. Maximum propagation delay would be probably around microseconds( 1-50 us). Transition time (rise + fall time) around 100-500 ns. \$\endgroup\$ – Jesse Haataja May 3 at 9:00
  • 2
    \$\begingroup\$ Disabling IC by removing VCC In a proper design, you really should avoid such a "solution" like the plague, not so much because of potential damage to the IC but because of unexpected behavior. You already learned about the ESD diodes. If you have a solution that works for you and the currents remain small then in my view nothing will be damaged and lifetime should not be an issue. Have you seen Dave's video about the ESD diodes: youtube.com/watch?v=2yFh7Vv0Paw&t=4s ? \$\endgroup\$ – Bimpelrekkie May 3 at 11:36

If your intention is to make sure that the voltage rails are nearly zero when enable is low, you'd have to drain the voltage store at these capacitive nodes, either passively or actively.

Passive Draining

Draining it passively is accomplished by connecting a resistor in parallel to the voltage rail of interest. A low resistor will lead to a continuous power loss in the system during normal operation, but will make sure to drain the node very rapidely once you disable the optocopler. For a highly resistive resistor, you would have to wait for some time until the supply voltage rails would go down to an acceptable level.

Since you are using \$15V\$ and \$5V\$ in your system, bleeder resistors would have to be connected to both rails. This approach is the easiest one and require small modifications, however, it has the drawback of adding additional power loss.

Active Draining

Implementing an active draining circuit, reduces the continuous power loss but it comes with the burden of adding more complexity. The idea here is that the nodes are only drained once you disable the optocopler. For the the \$15V\$ rail it would look like something like:

Here, the \$V(out)\$ which represents your \$+15V\$, is drained through a \$100\Omega\$ resistor and a pair of MOSFETs. The draining "speed" can be configured through the active bleeder resistor \$R_3\$.


| improve this answer | |
  • \$\begingroup\$ I dont know if you understood me right but it should also work if I still have 5V pulses at the input while enable is 0 (vcc +5 and +15 are floating). \$\endgroup\$ – Jesse Haataja May 3 at 9:21
  • \$\begingroup\$ If I understood you correctly, you would need to implement the same thing in the 5V rail as well, to make sure that these spikes are not seen by your ICs. \$\endgroup\$ – vtolentino May 3 at 9:59

I once inherited a design that had this issue. I solved it by clamping the switched voltage to ground when not enabled. You could do this with a second opto-MOSFET, but connect its diode anode to +5V so the logic is reversed. You probably want a small value resistor in series with the second opto, maybe 10-30 ohms, so you don't stress your power source during the transitions.

Now you will stress the ESD diodes more, since they will be driving a lower impedance. A small resistor in series with the inputs can solve that. You will need to find a value that still allows the circuit to work without stressing the input diodes too much, maybe a few hundred ohms.

| improve this answer | |
  • \$\begingroup\$ For this answer also I dont know if I was clear enough. While the IC:s are disabled by making vcc float there might still be pulsed 5V input. By clamping both of the VCCs to gnd makes current quite high for the device that is driving my input pins right? \$\endgroup\$ – Jesse Haataja May 3 at 9:30

Pulling the Vcc pin to GND could be a solution:


simulate this circuit – Schematic created using CircuitLab

The totem-pole drive stage consisting of Q2 and Q3 is a buffer with a very low output impedance. I've marked Q2 and Q3 as general-purpose BJTs but they can be MOSFETs. Rb prevents the input to be floating, which can be 10k or so.

When the EN signal is high, a non-zero current through the opto's transistor will trigger the totem pole so the Vcc will be +15V. When the en signal is low, the totem pole's input will be pulled down via Rb and so the Vcc pin will be effectively shorted to GND.


The circuit above shorts the IC's Vcc pin to GND but it's still dangerous if the inputs are non-zero when the Vcc is grounded. Probably the inputs have clamping diodes, so when you apply non-zero inputs those diodes may fry out -- this is also dangerous for the pins outputting those signals.

| improve this answer | |
  • \$\begingroup\$ Putting series resistors in the signal lines that could be high while the supply is off would be an option, as long as they ensure that the current that flows is lower than both the maximum source current of the upstream IC and the maximum safe current for the ESD diodes. But this could be an issue with very fast signals as it will slow rise/fall times. \$\endgroup\$ – SomeoneSomewhereSupportsMonica May 3 at 10:33
  • \$\begingroup\$ This can work, but please note that when using BJTs (or FETs) in this configuration, you will only have 15 V - (a saturation voltage + a threshold voltage). With BJTs I expect around 1 V, while with FETs it can be even more. \$\endgroup\$ – Vladimir Cravero May 4 at 7:09

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.