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Below is the schematic of a CMOS level 2to1 multiplexer. As you can see that if we want to choose A0, we set S input as Logic-0. CMOS level 2to1 multiplexer

My question is that what happens if we remove one transistor from each path. PMOS from C0 path, and NMOS from C1 path. Doesn't the circuit work without them as well?

The schematic is taken from Yamin Li's Computer Principles and Design in Verilog HDL book.

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Doesn't the circuit work without them as well?

No it does not, the PMOS + NMOS circuit is called a passgate or transmission gate. So this circuit has two passgates, C0 and C1.

In order to be able to conduct a high signal, the PMOS is needed (then the NMOS does nothing).

In order to conduct a low signal, the NMOS is needed (and the PMOS does nothing).

Only when a signal is "in the middle" both NMOS and PMOS conduct the signal. Note that in digital (logic) circuits the signal should never be "in the middle".

As we do not know if the input signal is either low or high, we have to support both low and high so an NMOS and a PMOS are needed.

For a more detailed explanation of the pass gate, look here.

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Consider this better diagram of the actual MOSFETs inside a transmission gate: -

enter image description here

Look closely and you'll see that the bulk connections for each MOSFET are not tied to their respective source nodes but to opposing power rails. This ensures that when a particular MOSFET is deactivated, the body diode that might normally conduct (and would ruin the "OFF" switching characteristic of the transmission gate) is reverse biased.

So, back to your question; if only one MOSFET was used, how would it handle the conditions of UA and UB that is handled nicely by other other MOSFET?

Say UA was high (the input) and the P channel MOSFET was removed, the remaining N channel MOSFET would not be able to turn on properly and so it wouldn't conduct very well and, basically, the device doesn't work properly.

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