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This is just a theoretical question I have. Imagine we have a register (a reg signal in Verilog for example) and two possible inputs that have to write to that register. I am assuming all signals are synchronous to the same clock. Normally in these cases I guess that you need a multiplexer to decide which signal actually go to the input of the register. But, it is possible to connect both signals to the input without any multiplexer? I am assuming that at all times only one source wants to write to the register. I have this question because I'm wondering if it is possible to avoid using the multiplexer and thus reducing resource usage in the final circuit.

Thank you in advance

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    \$\begingroup\$ Please remember that declaring something to be a reg does not mean that you will infer a clocked register. This was an unfortunate naming convention that was built into Verilog. A reg is just a variable datatype. \$\endgroup\$ – Elliot Alderson May 3 at 13:18
  • \$\begingroup\$ Outside of an FPGA, you might accomplish this with tristate drivers, ie those that can be "disabled" when it is not their turn to drive high or low. The classic example would be a computer expansion bus. But this is generally discouraged inside an FPGA or ASIC, because multiplexers are cheap, and tristate solutions tend to be slower. Today even in PCs true busses are rare, most high speed data connections are actually one driver feeding one receiver. Tristate buses survive in slower housekeeping tasks like SPI and (in a sense) I2C. \$\endgroup\$ – Chris Stratton May 3 at 16:50
  • \$\begingroup\$ Yes, I know @ElliotAlderson. I was assuming that the reg signal was already clocked, thanks for the clarification. \$\endgroup\$ – jdeharor May 4 at 6:48
  • \$\begingroup\$ And also thanks to @ChrisStratton for the answer, I understand now that I have to use multiplexers since my target are ASIC and FPGAs. \$\endgroup\$ – jdeharor May 4 at 6:48
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It's possible to do this in certain technologies, like bipolar open collector and custom cmos. But you won't see this available for most synthesis tools to implement directly in and FPGA or ASIC.

With open collector, you declare a net as tri1 or a wire with an attached pullup. Or you can use the wand net directly. Each open collector driver can pull the net to 0, but all have to be off to have the net be 1. I2C protocol uses this technology for intra-board communication. There are other technologies that give you a wire-ed NOR.

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  • \$\begingroup\$ Thanks! I see that my aim is not to use this technology, and use multiplexers instead. \$\endgroup\$ – jdeharor May 4 at 6:56
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Simple answer, no.


Longer answer, ask yourself the following question

  • How would you connect multiple outputs to the same input in a logic circuit?

You need some form of signal combiner. That combiner is an N:1 multiplexer.

You can sometimes simplify the multiplexer if you can guarantee certain things about the incoming signals. For example if you know that the signals will always be zero unless they are the one writing, then you could use a simple OR gate. However synthesis tools are usually pretty good at making this optimisation themselves.

If this is for an FPGA, then the registers are built in logic slices usually containing some form of lookup table (LUT). It's that LUT that is used to combine the signals - configuring that LUT as a simple 2:1 multiplexer (assuming a >= 3bit LUT) uses up no more resources than a simple OR gate. So trying to optimise manually just results in harder to read code for no benefit, and increases the likelihood of mistakes.

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  • \$\begingroup\$ Yes, I asked myself that question but since I am not an expert of this field I was not sure about the answer. I mean I know multiplexers are the solution but didn't know if it would work to just join the two signals without any logic element in between. Also thanks for the answer! I will keep up with multiplexers. \$\endgroup\$ – jdeharor May 4 at 6:53

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