This is just a theoretical question I have. Imagine we have a register (a reg signal in Verilog for example) and two possible inputs that have to write to that register. I am assuming all signals are synchronous to the same clock. Normally in these cases I guess that you need a multiplexer to decide which signal actually go to the input of the register. But, it is possible to connect both signals to the input without any multiplexer? I am assuming that at all times only one source wants to write to the register. I have this question because I'm wondering if it is possible to avoid using the multiplexer and thus reducing resource usage in the final circuit.
Thank you in advance