Is it possible to have a register with multiple drivers?

Question

This is just a theoretical question I have. Imagine we have a register (a reg signal in Verilog for example) and two possible inputs that have to write to that register. I am assuming all signals are synchronous to the same clock. Normally in these cases I guess that you need a multiplexer to decide which signal actually go to the input of the register. But, it is possible to connect both signals to the input without any multiplexer? I am assuming that at all times only one source wants to write to the register. I have this question because I'm wondering if it is possible to avoid using the multiplexer and thus reducing resource usage in the final circuit.

Thank you in advance

Answer 1

It's possible to do this in certain technologies, like bipolar open collector and custom cmos. But you won't see this available for most synthesis tools to implement directly in and FPGA or ASIC.

With open collector, you declare a net as tri1 or a wire with an attached pullup. Or you can use the wand net directly. Each open collector driver can pull the net to 0, but all have to be off to have the net be 1. I2C protocol uses this technology for intra-board communication. There are other technologies that give you a wire-ed NOR.

Answer 2

Simple answer, no.

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Longer answer, ask yourself the following question

• How would you connect multiple outputs to the same input in a logic circuit?

You need some form of signal combiner. That combiner is an N:1 multiplexer.

You can sometimes simplify the multiplexer if you can guarantee certain things about the incoming signals. For example if you know that the signals will always be zero unless they are the one writing, then you could use a simple OR gate. However synthesis tools are usually pretty good at making this optimisation themselves.

If this is for an FPGA, then the registers are built in logic slices usually containing some form of lookup table (LUT). It's that LUT that is used to combine the signals - configuring that LUT as a simple 2:1 multiplexer (assuming a >= 3bit LUT) uses up no more resources than a simple OR gate. So trying to optimise manually just results in harder to read code for no benefit, and increases the likelihood of mistakes.