In call instruction there are 5 machine cycles S,R,R,W,W (S is 6 T-states opcode fetch) and thus 18 T-states In first machine cycle, t1-t4 is utilized for fetching the opcode and decoding it and t5-t6 is used for decrementing the Stack pointer to facilitate pushing of higher byte of PC onto stack in 4th machine cycle . Now in conditional CALL instructions there are also 5 machine cycles S,R,R,W,W The T-states are given as 9-18 So if condition fails only first two machine cycles are executed . Therefore 2nd machine cycle is used for checking the flags in addition to being used for reading from memory . My question is that if condition fails , then first two machine cycles are executed , which means that in first machine cycle SP will be decremented by 1 but nothing will be pushed as only half of instruction is executed Won't this create incorrect operation of stack ?

  • \$\begingroup\$ What makes you think that the SP is decremented in the first cycle? \$\endgroup\$ – the busybee May 4 '20 at 8:25
  • \$\begingroup\$ Why else would it have 6 T-states instead of 4? \$\endgroup\$ – Bisma May 4 '20 at 9:25
  • \$\begingroup\$ Perhaps to fetch and check the flag? To keep the state machine simple? And even if the decrementer is used, the result does not need to be stored. \$\endgroup\$ – the busybee May 4 '20 at 10:04
  • \$\begingroup\$ If the flags are checked in first machine cycle itself ....then it knows here only that condition has failed .....why does it execute second machine cycle then ? \$\endgroup\$ – Bisma May 4 '20 at 10:22
  • \$\begingroup\$ Who knows? Such a person could linger around here, so let's wait. All we could do in the meantime is to guess and speculate, and that leads nowhere. \$\endgroup\$ – the busybee May 4 '20 at 10:28

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