In order to build a sensitive application, I am struggling to understand the behavior of the bias (and offset) current in oamps. I always thought unconsciously that the input terminals of the oamp act more or less like a current source, and that the bias+offset current is the current sunk. In fact, this may well be what LTspice thinks because the results of simulating the schematic below is a constant current through the cap (until Vcc+ is reached and then the current falls to 0).
The schematic below is a method proposed in the Art of Electronics to measure the bias current of very low bias current oamps. They says that this "worked well" for them. According to the book, the bias current is simply proportional to the voltage increasing rate by unit of time at the output terminal, which is easy to understand and seems also to enforce the idea that the oamp sinks a constant current.
Now, is this true? (question 1)
I've built the previous schematic and tested many different oamps. It appears that the truth is seemingly far from being that simple:
First, the voltage increasing rate at the output terminal is never linear, but seems to follow an exponential decreasing rate (like charging a cap at a constant voltage).
In one oamp (seemingly an imitation of the TLC662), the output voltage stabilizes about 1 V below Vcc+. In the other oamps (OPA627, TLC2272 and other), the output voltage stabilizes somewhere between 0 and Vcc+, and this threshold depends upon Vcc+; for example, for the OPA627, at 8V, the threshold is about 1.5V. At 20V, it is about 3V.
So, I looked at the schematic of the OPA6627 in the datasheet, I found that the input terminals are the gates of Jfets. This appeals the following 2d question: How is the gate of a jfet supposed to sink any current, except, perhaps, a few femtoamps due to leakage through the dielectric insulators, and disregarding the terminal capacitance loading ?
I would be happy to get thorough explanations of the oamp behavior described here.