# Fine points about the nature of bias current in oamps and experiments

In order to build a sensitive application, I am struggling to understand the behavior of the bias (and offset) current in oamps. I always thought unconsciously that the input terminals of the oamp act more or less like a current source, and that the bias+offset current is the current sunk. In fact, this may well be what LTspice thinks because the results of simulating the schematic below is a constant current through the cap (until Vcc+ is reached and then the current falls to 0).

The schematic below is a method proposed in the Art of Electronics to measure the bias current of very low bias current oamps. They says that this "worked well" for them. According to the book, the bias current is simply proportional to the voltage increasing rate by unit of time at the output terminal, which is easy to understand and seems also to enforce the idea that the oamp sinks a constant current. Now, is this true? (question 1)

I've built the previous schematic and tested many different oamps. It appears that the truth is seemingly far from being that simple:

First, the voltage increasing rate at the output terminal is never linear, but seems to follow an exponential decreasing rate (like charging a cap at a constant voltage).

In one oamp (seemingly an imitation of the TLC662), the output voltage stabilizes about 1 V below Vcc+. In the other oamps (OPA627, TLC2272 and other), the output voltage stabilizes somewhere between 0 and Vcc+, and this threshold depends upon Vcc+; for example, for the OPA627, at 8V, the threshold is about 1.5V. At 20V, it is about 3V.

So, I looked at the schematic of the OPA6627 in the datasheet, I found that the input terminals are the gates of Jfets. This appeals the following 2d question: How is the gate of a jfet supposed to sink any current, except, perhaps, a few femtoamps due to leakage through the dielectric insulators, and disregarding the terminal capacitance loading ?

I would be happy to get thorough explanations of the oamp behavior described here.

• JFET gates are junctions (hence the name) and will draw current when sufficiently forward biased. Also note that most opamp input stages change behaviour when inputs are sufficiently close to either supply rail; in ways that depend on the details of the input stage. Start with C2 charged to Vcc/2 (or 0V with +/- supplies) to see the AoE behaviour. – user_1818839 May 4 '20 at 12:14

The LM358 inputs are the bases of PNP transistors, so they source current related to the bias current of the front end. This will be a more-or-less constant current within the common mode range of the amplifier. If you go outside the CM range, the transistor may be biased off and won't source as much base current. This is generally true of bipolar-input op-amps, though some may sink current rather than source it (eg. everyone's favorite, the LM741). Here is the expected behavior of the input: as you can see it's close to -10nA (sourcing) near 0V common-mode voltage, with only a +/-25% variation for voltages between -14V and +12V (with +/-18V supplies).

MOSFET-input amplifiers leak very little current across the insulator- what leakage there is will mostly be related to the protection network on the chip (usually not well documented). The TLC2272 schematic shows a differential pair of MOSFETs but there is a protection network on each input pin, and the single MOSFETs are probably each an array of individual transistors.

JFETs have an isolation junction so that will leak, but often the current is rather small.

• So, this explains the behavior for PNP or NPN based oamp. But it is still unclear why most FET amplifiers sink at an exponential rate, and stabilize at some voltage in between. – MikeTeX May 4 '20 at 13:31
• Imagine a protection network that is something like two reverse-biased diodes between the supply rails, and each is leaking a bit. – Spehro Pefhany May 4 '20 at 13:34
• Ho I see. Good! – MikeTeX May 4 '20 at 13:35

the oamp sinks a constant current. Now, is this true? (question 1)

Depends on the op amp.

First, the voltage increasing rate at the output terminal is never linear, but seems to follow an exponential decreasing rate (like charging a cap at a constant voltage).

The LM358 sources almost constant current up to ~1.3 V below Vcc (the upper common mode input voltage limit), producing a linear voltage ramp.

In one oamp (seemingly an imitation of the TLC662), the output voltage stabilizes about 1 V below Vcc+. In the other oamps (OPA627, TLC2272 and other), the output voltage stabilizes somewhere between 0 and Vcc+, and this threshold depends upon Vcc+; for example, for the OPA627, at 8V, the threshold is about 1.5V. At 20V, it is about 3V.

Depending on the configuration of the input stage, bias current variation with common mode input can be quite non-linear. 'Rail to Rail' bipolar input op amps have complementary transistors which cause the bias current to jump from negative to positive as input voltage crosses the mid-point.

How is the gate of a jfet supposed to sink any current, except, perhaps, a few femtoamps due to leakage through the dielectric insulators, and disregarding the terminal capacitance loading ?

There is only leakage current in a FET Gate, but in the OP627 it can be up to 10 pA at 25 °C and 50 nA over the operating temperature range. This is not reliable. Some bipolar input op amps have lower and more predictable bias current at high temperature!