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Is it possible to debug an I2C bus effectivaly with a two channel (plus an external trigger) oscilloscope? I've been trying to do it, to catch a single transaction starting from the start until the end, but I find it hard to set a trigger properly on the scope.

Is it possible to build some kind of logic AND gate with SCL & SDA as inputs, and feed the output to the external trigger ?

Note: I have a simple 2 channels digital scope, with no extra features.

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If you can control the code in the i2c master (I presume this is related to your previous question, using a MCU), I can see two easy options that do not require any hardware outside of your current setup to generate the trigger:

  • Use any extra pin you may have (or temporarily repurpose an existing one): Assert it right before i2c transactions, deassert it right after.
  • Insert a known delay between transactions, and trigger on pulse longer than said delay on the scl line.
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  • \$\begingroup\$ Assertion of a seperate line, so simple... how didn't I thought of it... thanks \$\endgroup\$ – Mellowcandle Nov 25 '12 at 6:10
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The easiest thing would be to trigger on the start condition. That is SDA falling while SCL is high. This could be detected with a D flip flop clocked by the falling edge of SDA and with SCL as the data input. The trigger will probably be reset some time during the message since SDA will likely wiggle. However, in those cases SCL should always be low. Set the scope to trigger on the rising edge of Q to trigger on the start of a message.

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Many newer digital scopes have the ability to decode I2C natively, and can be set up to trigger on a variety of conditions. Shame about yours. (What scope are you using, by the way?)

If there's sufficient bus-idle time (SCL and SDA high) before the event, you could simply do a one-shot capture of the first edge of SDA going low, which would correspond to the start event. Make sure you have the trigger timebase near the left edge of the screen to capture maximum data.

If your scope can do a little more advanced triggering, you could look for the falling SDA edge while SCL is high, which would prevent false triggers on data transmission (i.e. not triggering when SCL is low and SDA changes, which is the norm other than for start/stop conditions).

Neither of these require the use of any external triggers or additional circuitry. You can use a D-latch to generate a start event trigger if you must go external - Q will go from low to high on a valid start condition. (I've not tested this, so YMMV)

image from esacademy.com

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