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Problem

I'm trying to simulate the simplest possible model for a flip-flop: two inverters connected in a circle. I'm using ngspice 31 on Arch Linux. I based my model on the CMOS SOI Inverter example (https://sourceforge.net/p/ngspice/ngspice/ci/master/tree/examples/soi/). Here is what I came up with:

SOI Flip-flop

.include ./bsim4soi/nmos4p0.mod
.include ./bsim4soi/pmos4p0.mod
.option TEMP=27C

Vpower VD 0 1.5
Vgnd VS 0 0

MN0 X Y VS VS N1 W=10u L=0.18u Pd=11u Ps=11u
MP0 X Y VD VS P1 W=20u L=0.18u Pd=11u Ps=11u
MN1 Y X VS VS N1 W=10u L=0.18u Pd=11u Ps=11u
MP1 Y X VD VS P1 W=20u L=0.18u Pd=11u Ps=11u

.ic V(X)=0 V(Y)=0
*.ic V(X)=1.5 V(Y)=1.5
*.ic V(X)=1.5 V(Y)=0
*.ic V(X)=0 V(Y)=1.5

.tran 2ps 2ns

.control
  run
  plot X Y
.endc

.END

This should correspond to this schematic:

schematic

simulate this circuit – Schematic created using CircuitLab

I want to see how this circuit behaves under different initial conditions for the gate voltages, especially metastable ones. (I know I could use NAND gates instead of inverters to make this into an actual RS flip-flop and produce metastable states with input pulses, but I'd like to use this simplest model if possible.)

Results

The stable initial conditions yield stable results as expected:

X = 1.5 V, Y = 0 V: X = 1.5 V, Y = 0 V

X = 0 V, Y = 1.5 V: X = 0 V, Y = 1.5 V

One of the metastable starting conditions also looks fine, with an initial metastable period and a stable outcome:

X = 1.5 V, Y = 1.5 V: X = 1.5 V, Y = 1.5 V

The other metastable starting condition, however, produces this:

X = 0 V, Y = 0 V: X = 0 V, Y = 0 V

This looks different, because the voltage overshoots to 1.6 V. A longer simulation time show that it takes about 2 us to settle to 1.5 V:

X = 0 V, Y = 0 V, 2 us simulation time

Now this is still fine, I didn't expect both cases to look the same. My problem is that the values change drastically when I change the simulation step size.

From 2 ps to 0.2 ps: X = 0 V, Y = 0 V, 0.2 ps simulation step size

To 0.02 ps: X = 0 V, Y = 0 V, 0.02 ps simulation step size

So a resolution of 0.2 ps increases the overshoot to 2.6 V, and a resolution of 0.02 ps seems to push both gate voltages to 3.75 V.

I experimented with the uic option for .tran and with .nodeset, but as far as I can tell from section 15.2 of the ngspice manual, the way I did it should be the right one.

Question

I am wondering what the issue here is. Is this naive simulation model, using only initial conditions, somehow inconsistent or wrong? How can a change of simulation resolution produce such different results? Or is this just not a suitable problem for a simulation because of the non-well-behaved nature of metastable states?

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  • \$\begingroup\$ Try using ever so slightly different values for the models, e.g. 11.01u or 10.99u, or other minor incosistencies that could appear in a real-life case. \$\endgroup\$ – a concerned citizen May 4 '20 at 18:27
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Setting arbitrary initial conditions isn't really "allowed," in that there's no realistic way that the circuit could ever get into that state. The sudden change between that takes place when the initial condition is removed from the circuit does not play well with simulators, as you have seen here. You could probably reproduce similar behavior using ideal switches.

You may want to try simulating with initial conditions around where you see the flat areas in your simulations, maybe around 0.5V or 0.9V, so there is not such a sudden change when the initial condition goes away.

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