So many answers I didnt read them all, being someone that sits on both sides of the fence, hardware and software....
So while in every way it is a programming langauge that gets compiled into other languages ideally lower level (C to asm or machine code, JAVA to bytecode or other langauge or assembly or machine code, etc). There are a lot more steps and the targets are much more varied than isa that are as common as they are different: add, mov, jne, push, pop, etc.
The machine code for fpgas or asics is not just discrete transistors, but a library of things. For asics for a particular foundry and process there is one or more cell libraries available and they will have simple and and or gates but also larger and more complicated things, why build a latch out of discrete components when the library authors can make some common sized ones and pack it up in an efficient (real-estate) way. So as with any compiler or high level author you go through the list of options and pick some. including a long list of srams of various widths and depths. For an FPGA it is LUTs or kinda fixed generic modules that can act as various modules that are more complicated than a simple and, or, xor gate.
The FPGA world likes to keep things close to their chest, also they try to be way more affordable than asic tools, tens of thousands of dollars per year rather than millions. And like any other integrated environment you at times have various vendors that were purchased or licensed and the tools glued together (often not very pretty).
So all the steps other folks mentioned happened. which is more than software does and the file formats are very proprietary and not expected to be documented nor supported, each version could change. Again these folks seem to be competitive and secretive (if they were to open up we could have significantly better tools and they could sell more product IMO, but may cut down on support money which is maybe what they live off of with their crappy tools).
When folks say netlist, the verilog is compiled into a netlist, the ones I have seen are also in verilog or vhdl as those languages cover that. ultimately you will then target the specific whatever, fpga, cpld, asic, etc. The fpga being an already wired/fixed target you ultimately end up with a list of fuses or switches if you will, take a generic lut and connect this input to that and that input to that by opening and closing connections in the massive mesh of stuff. Which ends up being a sorta simple list of ons and offs. And I think there may be a jedec standard on this but often called a bitstream and at least we use a bitstream player to load.
CPLDs in general you program this information in the part itself be it a flash on board that then opens/closes things on power up and/or the non volatile storage inside powers up with the items wired.
FPGAs typically have an external flash and on power on the information to connect things is loaded from that then the rest of the part comes up using that setup. The ones I know about you can while powered also load this information into the part and make all the connections, but that information is lost when the part is powered down. so depending on your design you might have some other solution and not use the flash. The flash format is probably prioprietary, I have not looked personally, when you come in through the programming interface that goes through the fpga to the flash so it could go as is or it could be converted on its way into something else.
With software esp this time and place we are used to mostly open stuff, somewhat good free tools that many folks use. Which also means the file formats are documented and somewhat common, some had history before this time .com and .exes and some others for other operating systems of the day. But again the software world is more common than different you ideally are aiming for machine code or bytecode. With logic you are going from high level to a lower level but using the same language to some point. Then you may be targetting a simulator which has its own library of modules or fpga n with its library or fpga m with its library and so on. And those folks are very protective of information.
Clifford and project IceStorm IMO is the right way to go, it is so far the only time I have built something for an fpga that is simple, it works, no warnings or errors which software folks often like. I have spent countless nights trying to get the simplest thing to build for an fpga from all the major vendors without warnings...and would always give up. From verilog to programmed part it is at least three separate projects which implies there are intermediate files that both sides need to support so the file formats are there. but would be expected to be project specific and not necessarily like an elf file that is widely used for more than one use case.
Understand that the chip world including fpgas is insanely expensive so it is money driven which often means sell tools and most importantly annual support contracts. Which means closed source, closed information, not publicly documented file formats.