I have a register which holds 12 bits written in VHDL within Vivado which is not being gated properly. The code is very simple, and is as follows:
library ieee; use ieee.std_logic_1164.all; entity reg12b is port ( reg_in : in std_logic_vector(11 downto 0); load, clock, clear : in std_logic; reg_out : out std_logic_vector(11 downto 0) ); end reg12b; architecture description of reg12b is signal internal_value : std_logic_vector(11 downto 0) := "000000000000"; begin process (clock, clear, load, internal_value) begin if rising_edge(clock) then if (clear = '1') then internal_value <= "000000000000"; elsif (load = '1') then internal_value <= reg_in; else internal_value <= internal_value; end if; end if; end process; reg_out <= internal_value; end description;
As you can see, this holds 12 bits, and has a synchronous reset function. This is what it synthesizes to in Vivado. As you can see in the blue highlighted line, the Flipflop is an input to the LUTs, but another input to the LUTs is the inputs. I've tried refactoring my code a large number of times, and it never seems like I can put the flip flops as the sole output.
How do I tell Vivado that I want it to design the second picture, and not the first picture?