# Current balance capacitor

Most series capacitors needs balancing resistors to keep the same voltage across them, but in my case, I'm using with three capacitors of 45uF in parallel that are working very close to its maximum RMS current rating. I'd like to know, is it necessary to put any resistor or inductor to balance the current of the capacitors? If so, could you please guide me on how to do that.

• It's difficult to understand your application. Are you feeding AC through these or is it for a DC power supply voltage smoothing? Post a schematic or add one using the CircuitLab button on the editor toolbar. Commented May 5, 2020 at 19:48
• I have some difficulties understanding the issue as well. Are you concerned with the current capability of the capacitors, i.e. any small difference between the parallel ones would lead to a higher current in one of them? That's why you would use "balancing resistors"? Commented May 5, 2020 at 20:39
• @HorrorVacui exactly. This capacitor bank will be charged with DC voltage and then switched to discharge onto a load. According to the datasheet the peak current is OK but its RMS current during the work period is very close to the rating. So I needed to be sure that the RMS current in each capacitor will be the same. Commented May 5, 2020 at 20:57
• See my commentrs on Neil's answer. Commented May 6, 2020 at 2:45

An exact answer would depend on many other factors, so it is possible that engineer A has an opinion which does not conclude with the opinion of engineer B.

• If possible, just buy a higher rated component.
• The rated operating parameters are stated for the all possible variations during production. Being at or slightly above the limit will not cause malfunction in most of the cases. It will have a finite probability though. You have to decide how much risk you are willing to take.
• If the caps are from the same rail, then they will have similar parameters with a very high probability, so unless there is a significant temperature gradient, no balancing is needed. Here was also an assumption, but a fair one.
• If none of the aboves are not the case, you should check the capacitance value accuracy and the ESRs and ESL. The PCB traces will contribute to it as well. Also a question is whether you would like to design for worst case, or just for acceptable yield. The last case would require some tests.

Note: that any resistance in series with the cap reduces its quality factor, and increase its losses, and reduce the peak currents it is capable of supply. So try to avoid it if possible.

Three capacitors in parallel will necessarily have the same voltage. As the charging current through each is C.dV/dt, they will also be necessarily equal, if the capacitances are equal.

That's at low frequency. At high frequency, the currents will split according to the impedances, which include the ESR and the ESL.

Unfortunately the OP has included no information as to the speed of the discharge (and the charge for that matter), or whether he is a hobbyist making a one-off, or a professional designer aiming to sell a product with a warranty, all of which are critical to the answer.

Unlike in a series connection, where imbalances in leakage current are dependent on dielectric impurities at very low levels, and so can vary by orders of magnitude between otherwise nominally identical components, the imbalances for a parallel connection, capacitance, ESR and ESL depend on geometry, and show much less variation between components. They are also likely to be stable, whereas leakage might be expected to vary wildly with time and temperature.

To see whether ESR, ESL or capacitance are going to dominate the RMS current, the nominal discharge and charge currents need to be determined, either by measurement, or modelling with SPICE into the specific load.

If the discharge RMS is shown by modelling to be strongly dependent on ESR, and if the chosen capacitor shows a large ESR variation between units, and if that variation is significant in terms of the ratings, then there are two approaches, swamping, and trimming. In swamping, you would connect a resistor in series with each capacitor an order of magnitude larger than its ESR. This them dominates the split of current. It's also likely to change your experimental setup, and need a redesign. The alternative is trimming, where you measure all the capacitors, and add external resistance to those measured to have low ESR.

Calculations for ESL would follow a similar, though more difficult to measure, path. As a first step, to keep the external inductance equal, you'd obviously wire your capacitors symmetrically with respect to the terminals, and not use a long bus fed from one end. A star arrangement would be best, or a long bus but fed from opposite ends.

With capacitance variation, there's no practical external balancing that can or should be done. In theory, a large external series capacitor could trim the net capacitance. In practice it would probably be more trouble than it's worth. You can't trim with external resistance, though you can swamp for the dependence on current. However, as R is at right angles to C, you'd need a significant series R, which would almost certainly change the discharge into the load, and need a redesign. I wouldn't suggest you try to trim the C with external L, unless you model it thoroughly, and know exactly what overshoots are going to do in terms of discharge current and capacitor overvoltage.

The only two practical responses to capacitance tolerance are to either derate the datasheet RMS current limitation by the capacitance tolerance to get your working limit, or to design for a significant and discharge determining series resistance to be used with each capacitor. Manufacturers of pulsed power equipment like spot welders and motor magnetisers use the 'designed with a series resistor' approach to allow the discharge to be well controlled, even in the presence of varying external inductance, which also means the capacitors can be guaranteed to be operated well within their limits.

Are you a hobbyist or professional? If a pro, then you already know the answer. Don't use those capacitors. Use more, smaller ones in parallel, and lower voltage types in series if necessary, until the calculated RMS current is far enough below the rating that you meet your customary derating factor.

If you are a hobbyist, then I'd say just go for it, as it is. By checking the specifications, you've already shown yourself to be far better than the typical power hobbyist, for which the mantra is 'turn it up until it catches fire, then back off a bit'. You may get a shorter life than expected from the caps, does that matter? That's not a flippant question, expected lifetime is a significant specification when designing power electronics.

• I'd like to query my esteemed colleagues (several) responses in this case. The OP is concerned about overall RMS current so charge and discharge may matter. Knowing the charge & discharge conditions is a good idea. If three substantial capacitors ate connected in parallel then a say sudden step discharge load will lead the Vcaps all identical but if cap ESRs, Rexternals, Linternal and L External all vary somewhat then the delta discharge impedance may differ. ... Commented May 6, 2020 at 2:43
• Worst case one cap (say in a bank of caps side by side physically but fed side on electrically may lead to higher charge and discharge peak and RMS currents. While I'd not expect the differences to matter in practice in most cases, minimisation of different paths may help. Commented May 6, 2020 at 2:43
• This answer does not considers capacitor parasitics and capacitance value variation, and thus missing the question of the OP. Commented May 6, 2020 at 22:29
• @HorrorVacui This answer now considers parasitics. Does it help? Commented May 7, 2020 at 4:56

No, when you put resistor in parallel it have load sharing behavior. Just put it close together and low resistance (thick pcb trace) if one of these have lower voltage current form other will flow to change to equilibrium or point simultaneously . It will response faster than any active or passive component.

• He considers adding resistors in SERIES to balance the current through the caps. Commented May 6, 2020 at 22:27

A significant factor in current handling capability relates to heating effect.
One way to ensure that small excesses in rated RMS current have minimal effect is to ensure that all 3 capacitors are well cooled thermally. Two easy methods of ensuring this are:

(1) Have short leads to wide copper traces over a Ground plane. The Gnd plane is needed so the hot traces can dump heat thru the PCB epoxy-fiberglass into the sheet of copper foil underneath. Then you may need METAL MOUNTING POSTS or METAL SLIDERS, to remove Gnd Plane heat to the metal case (or chassis of the satellite). Decades ago I worked on satellite systems; we always had heat removal guys advising/mandating the foil coverage, so heat would flow to the PCB edges where the card cage sliders (or equivalent) passed the heat to the outside.

(2) Have good air access - either passive air flow or if a fan is present try to provide some moving air.

An usual but useful and occasionally used concept is to add external heatsinks to capacitors with high peak currents.

• see my comments on Neil_UK's answer. Commented May 6, 2020 at 2:44
• +1 Edited. Answer was OK as was albeit a bit terse. Downvotes not appropriate. Commented May 6, 2020 at 2:45
• Quite a change in votes. From -5 to 0 with 4 current downvotes. Shouldn't have happened. Commented May 6, 2020 at 23:50