I've recently just implemented a pseudo random number generator. This one to be more precise: http://www.cr31.co.uk/stagecast/trains/tt9_rng.html. Of course, for the sake of my experiment, it's random enough. I use it to "randomly" assign 0 / 1 to an output. The issue is that, due to the propagation delay that comes with the setup, I can't properly count the times when output is 1 or output is 0. Theoretically it should be 50/50. With this pseudo rn generator, because it has 31 states, the occurrence of 1 is 16 and of 0 is 15.

I have to specify that I need a way to generate the random variable using only logic gates.

The question is: Can I determine the propagation delay of the setup presented above? Is there an alternative to pseudo generate using only logic gates? with or without delay?

  • \$\begingroup\$ Welcome to the site. Please can edit your question and expand it considerably with details as its impossible to answer at present. Add the information pointed to by the link, so readers can see all of your question in one place. The shouldn't have to follow a link that may break in the future. Explain your implementation (logic gates, HDL, programming language) and why you have it. The better the quality of your question, the better the quality of the answers you will attract. Again, a very warm welcome. \$\endgroup\$ – TonyM May 6 at 7:05

Your example is quite primitive compared to PRSG's with more entropy and better characteristics, but you need to define more than just latency as all buffers add latency.

PRNG's of order n all have one state out of the maximal length of the possible 2^n states that is invalid.

Using XOR vs XNOR allows you to choose that invalid state, so you MUST avoid it for the initial condition. Namely $00 for XOR and $FF for XNOR where the generator appears stuck.

You chose something other than this invalid state as the initial condition such as a certain seed value or a SET or RESET.

The latency is always the n value of the bits in the register. It is normally used with a large n >7 so the DC component is negligible or the offset between the total number of 1's and 0's for a long frame of bits between resyncs to eliminate the DC component.

Without a special seed, otherwise, it is impossible to balance this but then with say 2^19, does it matter?

The other thing to consider in latency is the entropy of previous bits in each burst or frame of data bits if it is not continuous.

Normally for each packet of data random generators are used for some channel requirement. If you need security or fast decoding or more error detection or correction , some use Chinese Remainder Theorem methods.

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The issue is that , due to the propagation delay that comes with the setup , i can't properly count the times when output is 1 or output is 0 .

I think you're doing something wrong:

This circuit is a clocked one. On every rising edge of the "CLOCK" signal, the flipflop takes up the value on the D input – after a while, it's got succesfully "stored" the new value, and after another while, the output has stabilized.

The sum of that's the time after each rising clock edge, at which everything is stable, can be read at the output, and the next rising clock edge could occur.

Now, at exactly the time when the clock goes high again, your output is still stable – it will just change after that instant in time.


Can I determine the propagation delay of the setup presented above?

yes, but you don't have to. You just read the output exactly at the rising clock edge.

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