I have been trying to understand the operation of the following polarity protection circuit (Diagram doesn't show the internal body diode of MOSFET):
There have been some posts on here (such as: MOSFET in reverse polarity protection and Reverse-polarity protection P-channel MOSFET) which detail the operation, however I wanted to make sure I have understood it correctly so I can try to apply it practically.
Firstly, the general operation of the P MOSFET with the polarity in the correct configuration (Shown above): e.g Zener diode voltage is 9.1V and power supply is 12V.
When a voltage is applied to the Drain pin (from V1), the FET is initially in the off state. Therefore current is passed over the internal body diode which raises the potential of the Source pin. When the source pin potential gets close to the reverse voltage of the zener, the zener diode begins conducting a very small current (Reverse current).
This reverse current increases as the Source pin potential rises, until the zener diode passes the maximum current permissible by the Resistor (R1). This raises the potential of the Gate pin and the FET will switch on when the Gate-Source voltage (Vgs) becomes more negative than the Gate-Source voltage threshold (Vgsth). When Vgs < Vgsth the FET will start to switch on and the current flowing across the internal body diode will decrease until the only current flowing is through the FET. (The maximum permissible current through the FET is determined by how much Vgs < Vgsth but it should only draw as much as the load connected to it).
So in summary, in the "steady state" there should be a 9.1V drop across the zener (which clamps the gate at 9.1V max) and the voltage drop across the Drain and Source pin should be given by the amount of current flowing (to the load) multiplied by the Rds value of the FET. (I've assume the current drawn by the zener resistor combination is negligible, is that correct?)
So in for the reverse polarity case:
The Drain pin is drawn to 0V, the zener has a forward voltage drop of approx 1.2V so the resistor should drop 10.8V. The Gate pin should therefore have a voltage of approx 1.2V and the Source pin should be at 0V. This means Vgs > 0 which means Vgs will never be less than Vgsth and the FET shouldn't turn on. (unless current could still pass through the FET somehow?)
So if I take a real world example, if we start with the following parameters:
- V1 = 12V
- M1 = P MOSFET (such as the AUIRF4905 listed here: https://docs.rs-online.com/b198/0900766b810c6926.pdf)
and the power supply is connected in the correct polarity, say I wanted to work out R1 and D1. Where do I begin?
From the FET datasheet:
- max Rds value = 0.02Ohm
- max Vgs = +/-20V
- max Vgsth = -4V
Do I choose the max Drain to Source current value I want from the FET datasheet (Fig 3) and read off the associated Vgs I need?
If I select a Zener Diode such as the 1N5346B (listed here: https://docs.rs-online.com/f6a4/0900766b814f43fb.pdf), from the datasheet:
- Reverse voltage is 9.1V (Vz nominal) when a reverse current (Izt) of 150mA is used.
- Forward voltage of 1.2V (Vf) if a forward current (If) of 1A is used
This means the voltage between the Gate and Source pins should always be -9.1V (which is within the max Vgs), which means (from FET datasheet Fig 3) I'll have a maximum permissible Drain to source current around 150A? (but the FET would burnout before I could theoretically reach that value?)
Then to work out the current limiting resistor, do I assume that with the FET turned on (with a sufficiently small Rds) that the voltage on the Source pin (taking into account the voltage drop through the FET channel) will be approximately equal to the source voltage? i.e 12V? Then the resistor value will be given by (V1-V(D1))/I(D1)? Which gives (12-9.1)/0.15=19.3 Ohm? If that is the case, then why is this resistance value so low when I've seen other examples use resistors in the kiloohm range? Have I done something wrong?
Sorry for the multiple questions, it feels like there are a lot of items to take into account...