1
\$\begingroup\$

In the lines wherever I try to do the assignment of value, the above error pops up. Please tell me what's the mistake and guide me with the corrected code snippet.

`timescale 1ns / 1ps

module big_small (


input [3:0] mant_A,
input [3:0] mant_B,
input [3:0] exp_diff,
input exp_diffsig,
input mant_diffsig,
output [3:0] big_mant,
output [3:0] small_mant
);




always@(*)

if (exp_diff == 4'b0000)
begin
big_mant <= (mant_diffsig)? mant_B: mant_A;
small_mant <= (mant_diffsig)? mant_A: mant_B;
end


else
begin
big_mant <= (exp_diffsig)? mant_B: mant_A;
small_mant <= (exp_diffsig)? mant_A: mant_B;
end


endmodule

\$\endgroup\$
1
  • 1
    \$\begingroup\$ left-hand side should be reg/integer/time/genvar - the left hand side of the <= assignment must be one of those four types. Is it? \$\endgroup\$ May 7 '20 at 11:04
3
\$\begingroup\$

The error says left-hand side should be reg/integer/time/genvar - in other words, on the line indicated, the left hand side of the <= assignment must be one of those four types.

Your left-hand side is declared as output big_mant (same goes for output small_mant) which are of type wire. You cannot do a procedural assignment (assignment inside an always statement or initial block) to a wire type as the error message has told you.

Change the two outputs to output reg types if you wish to use them as the left hand side of a procedural assignment statement.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.