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I simulated both ones and could not see any difference in functionality. So, what is the need for that extra NOT gate? When it is preferred?

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    \$\begingroup\$ That's a latch, not a D flip-flop. When E or CLK is high, the data passes through. A D flip-flop has outputs that only change on a particular clock edge (rising or falling, depending on the design). \$\endgroup\$ May 7, 2020 at 17:46
  • \$\begingroup\$ @SpehroPefhany hmmm, ok, then it should be edge triggered to be a flip flop, thanks, noted. Any idea on the use/necessity of that NOT gate? \$\endgroup\$
    – muyustan
    May 7, 2020 at 18:01
  • \$\begingroup\$ It is obvious the two circuits are equivalent... but more important questions are, "What is the idea behind them?", "For what purpose were they created?". Related questions are, "Is it possible to create an asynchronous D latch? Is it possible to create a synchronous RS latch? Does it make sense?" \$\endgroup\$ May 8, 2020 at 15:55
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    \$\begingroup\$ @Circuitfantasist nice questions to think about \$\endgroup\$
    – muyustan
    May 8, 2020 at 16:27

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If you look closely at the circuits, the pin the NOT gate is driving is driven from the output of the NAND gate in the other circuit. Basically, they get a NOT gate for free with the NAND gate, and they're making use of it.

When is it preferred? I would say never. If it is possible to get the same functionality without the NOT gate without affecting performance, then there is no reason for it. Additionally, removing the NOT gate decreases the load on the input, and it only results in that one NAND gate driving two pins instead of one. However, at the same time, nobody builds latches or flip flops from logic gates these days, instead more optimized, transistor-level circuits are used to increase performance and reduce area.

If you're working with 7400 series logic, you would use a 7475, 7477, or similar latch or flip-flop chip, which gives you multiple latches in one chip instead of using a whole 7400 quad NAND gate chip for one latch.

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They are more-or-less equivalent but the timing is not identical, especially for data stable and runt pulses on E in the second circuit. There may be other differences you can find.

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  • \$\begingroup\$ +1: For mentioning timing. \$\endgroup\$
    – copper.hat
    May 8, 2020 at 2:25
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They are logically equivalent. The only apparent difference is at the bottom left NAND gate. For the top circuit the output of this NAND gate is obviously $$ \overline{\overline{D}\cdot CLK}$$

In the bottom circuit the output of the NAND gate is $$\overline{\overline{(D\cdot E)}\cdot E} = \overline{(\overline{D}+\overline{E})\cdot E} = \overline{\overline{D}\cdot E + \overline{E}\cdot E} = \overline{\overline{D}\cdot E}$$ which is the same logic function if you substitute \$E\$ for \$CLK\$.

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    \$\begingroup\$ Nice demonstration on how they are equal to each other mathematically. \$\endgroup\$
    – muyustan
    May 7, 2020 at 18:30
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Probably, the first circuit was formally synthesized by a theorist who was not interested in how it would be implemented... while the second circuit was invented by an engineer who knew about the existence of 7400... This was exactly the reason we were guided by in the 90's, when we made setups for investigating various latches and flip-flops in the laboratory on digital circuits...

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    \$\begingroup\$ Quad nand2 chip? \$\endgroup\$
    – muyustan
    May 7, 2020 at 20:18
  • \$\begingroup\$ And apparently nobody heard of the 7475/7477, because that gives you four not-quite-independent D latches in one chip \$\endgroup\$ May 7, 2020 at 21:09
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First of all, you have wrong labels of CLK and E:

The first one has E (enable), not CLK. The output is dependent on level - Q copies D anytime when E is high.

The second one has CLK, not E. The output is dependent only on rising edge - Q copies D only when CLK is giong LO -> HI. When CLK is HI (or LO) and D is changed, it is not copied to Q. This circuit as is drawn is prone to oscilations.

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