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enter image description here

Here, I modify the encapsulated area of an SR latch(with NOR gates). The encapsulated area on the first circuit(with the NORs) is equal(at least, I think so) to the wider encapsulated area in the below circuit. So, I think that my inputs can be and should be used in the same order without changing it.

The BLUE ENCAPSULATED area represents the same SR latch again, but with R' and S' are used as input names and those NOT gates are eliminated. Eveything seems fine till here, however, at everywhere else, I see SR latch created with NAND gates as follows:

enter image description here

The difference of these with my drawing is the ordering(up to bottom) of S' and R'. And unfortunately, this one is the one which is correct and mine is wrong.

So, where do I do a mistake? Is there a conceptual misunderstanding in my thoughts?

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You have eliminated the NOT gates by moving the inversion to the outputs of the AND gates, thus changing them into NAND gates. But the two outputs Q and Q' are now no longer connected to the AND outputs, but to the NAND outputs, so they have the opposite value, and you have to relabel them as Q' and Q.

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  • \$\begingroup\$ yes.... I moved inversion bubbles towards gate outputs but forgot that they are also before Q and Q'. Thanks. \$\endgroup\$ – muyustan May 7 '20 at 14:14

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