How having separate instruction and data memories helps in implementing a single cycle data-path for mips instruction set? i want to know why we can only use data-path element once in a cycle for making the data-path capable of executing any instruction in a single cycle?

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    \$\begingroup\$ How could you use the datapath twice (more than once) in the same cycle? Be specific. \$\endgroup\$ – Brian Drummond May 8 at 10:42
  • \$\begingroup\$ @BrianDrummond why can't we use a functional unit twice in the same cycle. Can't we use that functional unit during some duration of the cycle and then again use it some other duration in the same cycle? \$\endgroup\$ – Karan Verma May 10 at 15:49
  • \$\begingroup\$ So ... sequentially. Then what distinguishes between those portions of a cycle? ... a faster clock. Which means you now have >= 2 cycles. You can only do this because your original cycle was too slow. \$\endgroup\$ – Brian Drummond May 10 at 17:22

Your question implicitally ask about a processor with separate instruction and data memory (and most of all: separate buses) compares to a processor with a shared instruction and data bus with regards to performance expressed in "number of cycles".

We should agree that a cycle refers to the clock cycle. We could also be talking about the instruction cycle. An instruction cycle can be multiple clock cycles, and instructions "always" execute in one instruction cycle.

However the goal of RISCs such as the MIPS is to execute one instruction per clock cycle.

There should not be any cycle faster than the clock cycle in the processor. Access to external memories can not be faster than that. If you have only one bus, you can load either an instruction or data in a single clock cycle, not both at the same time. So if your instruction is a load, you would first fetch the instruction, décode it, and the proceed with the load. That would require two clock cycles.

By separating the buses, you can read an instruction and data in a single cycle. So every cycle can read an instruction as well as read or write data. Without this, you can not do it in a single cycle.

Separating buses alone is not enough. You could have a shared memory space, but your memory needs to have two interfaces that allow access to two different locations at the same time. With separate memories you immediately have the possibility to put them on separate buses, if not the memory architecture is more complex.

It is not because you can access instructions and data at the same time, that the data is related to the instruction that is read at the same time. It can very well relate to the previously read instruction. For instance a first instruction can perform a LOAD from memory to R1 (register1), and the second instruction could add 4 to R1 which would hold the loaded value "at the same time" as the second instruction is fetched - just in time to add "2" to this loaded value.

To be clear about your second question "why we can use the data-path element only once in a cycle?", as explained above, you can do only one memory access in a clock cycle because that is the "fastest" cycle in your system.

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