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The common idea for a stripline is that the trace is sandwiched between two ground planes.

My question: is it the same, for the purpose of characteristic impedance, to have a ground plane or a power (VCC) plane? That is, would the stripline's characteristics be the same if I sandwich the trace between GND/GND, or between GND/VCC, or even VCC1/VCC2?

My instinct is that it should be the same, since for small-signal analysis VCC is the same as GND. And as I understand it, characteristic impedance aspects go with small-signal analysis. However, I'm not sure that this is the case. Plus, even if it is the case: are there any requirements on the geometry or decoupling for the power plane(s)?

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  • \$\begingroup\$ your power plane would porbably be an RF ground, so I would say yes, it is the same. \$\endgroup\$
    – Joren Vaes
    May 8, 2020 at 12:22
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    \$\begingroup\$ As the given answer says, this isn't a problem for the transmission line. But be careful how you connect the transmission line to the source and load. Remember that the return current connection is just as important as the signal connection. \$\endgroup\$
    – The Photon
    May 8, 2020 at 14:22
  • \$\begingroup\$ @ThePhoton ‒ not sure about the second part of your comment; if it is a differential pair, they should be tightly coupled, and one line is the return for the other. And for single-ended, the two planes would act as return paths, no? As long as the stripline doesn't cross slits / large-holes in the planes (which as a "master rule", it should not), I should be fine, correct? \$\endgroup\$
    – Cal-linux
    May 8, 2020 at 20:00
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    \$\begingroup\$ Right, but you can't just connect the ground pin of a chip to the power plane. If the chip provides a termination between signal and ground, but your transmission line used power as the return conductor, you need to provide a path for the return current to get from the ground pin of the chip to the power plane. This might just be the bypassing capacitor of the chip power supply, but if the frequency is high, or the power plane you used doesn't connect to this chip then you need to do something else to complete the return path. \$\endgroup\$
    – The Photon
    May 8, 2020 at 20:08
  • \$\begingroup\$ @ThePhoton ‒ At first, I thought I perfectly understood what you're pointing out. However, the only way I can picture an example of the problematic scenario you describe is if there was galvanic isolation. I'm also puzzled about: why would the transmission line use power as the return conductor? Being a stripline, it is running with both the ground plane and the power plane always adjacent. Is it that you just meant to be careful not to interrupt the ground plane? (but we have to be careful with that anyway, right?) Or just careful not to do anything weird with the connections? \$\endgroup\$
    – Cal-linux
    May 9, 2020 at 1:46

1 Answer 1

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My question: is it the same, for the purpose of characteristic impedance, to have a ground plane or a power (VCC) plane?

It's the same - Vcc planes are highly capacitively connected to ground planes and, if not, they should be. So, they behave identically for the calculation of characteristic impedance.

Plus, even if it is the case: are there any requirements on the geometry or decoupling for the power plane(s)?

Yes, decoupling the Vcc plane to ground needs to be done at regular intervals along the length of the stripline. Probably (for best effect) at distances not greater than \$\lambda\$/10 but this can vary.

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  • \$\begingroup\$ Interesting. So, am I understanding correctly that I would need to place extra decoupling capacitors just "in the middle of nowhere" with one terminal via'd to GND and the other terminal via'd to the power plane? Same thing if the stripline goes between VCC1 and VCC2? I guess I could decouple VCC1‒VCC2, instead of decoupling VCC1 to GND and VCC2 to GND? [[ By "in the middle of nowhere", I mean just in the middle of the copper pours, not between VCC and GND pins of some IC requiring decoupling ]] \$\endgroup\$
    – Cal-linux
    May 8, 2020 at 20:06
  • \$\begingroup\$ It’s only when the wavelength and length of the track is sufficiently long that “nowhere” actually becomes “somewhere” important so as not to make an unintentional Patch antenna out of the power plane. \$\endgroup\$
    – Andy aka
    May 8, 2020 at 21:20
  • \$\begingroup\$ @Cal-linux The capacitor formed between the ground and power planes is a high quality capacitor (low inductance & ESR) which augments the capacitors used for bypass. \$\endgroup\$
    – qrk
    Oct 21, 2021 at 20:14

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