I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to provide operand values to the adder and to store the calculated output at each posedge clock. When I try to do it as shown below, the output is delayed by one clock cycle. Is there any way to modify the code so that the output registers are updated with the results in the same clock cycle as input registers? I am new to Verilog and I don't totally understand different types of assignments. Also, I will be synthesizing this design later.
module four_bit_hca_reg( clk, S_out, C_out, A_in, B_in, C_in); input [3:0] A_in, B_in; input C_in, clk; output [3:0] S_out; output C_out; reg [3:0] A, B, S; reg Cin, Cout; wire [3:0] Sum_wire; wire Carry_out_wire; four_bit_hca adder (.A(A), .B(B), .Cin(Cin), .S(Sum_wire), .Cout(Carry_out_wire)); assign S_out = S; assign C_out = Cout; always @ (posedge clk) begin A <= A_in; B <= B_in; Cin <= C_in; S <= Sum_wire; Cout <= Carry_out_wire; end endmodule