How does assignment work in Verilog?

Question

I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to provide operand values to the adder and to store the calculated output at each posedge clock. When I try to do it as shown below, the output is delayed by one clock cycle. Is there any way to modify the code so that the output registers are updated with the results in the same clock cycle as input registers? I am new to Verilog and I don't totally understand different types of assignments. Also, I will be synthesizing this design later.

module four_bit_hca_reg(
    clk,
    S_out, C_out,
    A_in, B_in, C_in);

input [3:0] A_in, B_in;
input C_in, clk;
output [3:0] S_out;
output C_out;

reg [3:0] A, B, S;
reg Cin, Cout;

wire [3:0] Sum_wire;
wire Carry_out_wire;

four_bit_hca adder (.A(A), .B(B), .Cin(Cin), .S(Sum_wire), .Cout(Carry_out_wire));
assign S_out = S;
assign C_out = Cout;


always @ (posedge clk)
begin

A <= A_in;
B <= B_in;
Cin <= C_in;
S <= Sum_wire;
Cout <= Carry_out_wire;

end

endmodule

Answer 1

Let's consider the timing of the sum output (the timing of the carry output will be analogous). You have 3 sum signals in your code:

• Sum_wire
• S
• S_out

Let's assume your clock period is 10ns and you drive all inputs at the posedge of clk in your testbench. When you run simulations, you will see S and S_out change at the same time as each other, and they will change 10ns after Sum_wire. That is what the always block does: adds one clock cycle delay to the Sum_wire signal. The always block will infer 4 D-flip-flops when it is synthesized, with Sum_wire bits as the D inputs and S bits as the Q outputs.

Regarding visibility, when you run simulations and dump waveforms, you can see all of the sum signals. If you really want to use the internal sum outside of the four_bit_hca module, you can add it as another output in the module port list.