I am a beginner in microprocessors. Apologies if my question is too naive.

The memory section of the 8086 processor is divided into two segments: even and odd to allow the CPU to fetch 16 bits in one clock cycle. When a 16 bit word is to be read from memory at an odd memory address say 125, the CPU first puts 124 on the address bus and gets the contents at location 125 in the higher order byte. In the next clock cycle the CPU puts 126 on the address bus and gets the contents at location 126 in the low order byte. These two bytes are then swapped by the processor because these values entered the CPU in the wrong half of the data bus.

The above operation takes 2 clock cycles. Why can't the CPU simply put the address 125 on the address bus and compute the next address and put the contents of that address ( 126 in this case ) onto the low order byte of the data bus? The low order and the high order byte can be swapped later allowing the processor to fetch a 16 bit value from memory in only 1 clock cycle.


3 Answers 3


Word-wide memory is addressed with a single address bus. When a word is read from an odd address, one byte is in one word, the other byte in another. You cannot address both bytes at the same time. Even if the memory had a separate address bus for each byte, the processor does not have the pins to address both address busses at the same time.


The book is slightly wrong, but let's try to clear it up. The thing is, you can put 125 on the address bus. But you cannot read addresses 125 and 126 in a single clock by doing so. Basically this is because the numbers 125 and 126 differ in bits other than the last bit.

The 8086 has 20 address lines (A19:A0) and 16 data lines (D15:D0). Actually the 16 data lines and the lower 16 address lines are the same pins, also called AD15:AD0. They function as address lines for the first part of the clock cycle, and data lines for the later part. Also important for addressing is a pin called BHE, "bus high enable". A0 also functions as an "enable" pin, as we'll see in a moment.

If the 8086 wants to read the word at addresses 124-125, It puts 124 on A19:A0, and sets BHE to low. Both banks of memory see the address on A19:A1, and since A0 and BHE are both active-low signals, both banks will be active. The upper bank will put data on D15:D8, and the lower bank will put data on D7:D0, and the CPU gets a full word.

If the 8086 wants to read a single byte at address 124, it puts 124 on A19:A0, and sets BHE high. Because A0 is low (active), the lower bank will put data on D7:D0, but with BHE high, the upper bank does nothing.

If the 8086 wants to read a single byte at address 125, it puts 125 on A19:A0, and sets BHE low. Because A0 is high, the lower bank is inactive, and because BHE is low, the upper bank will put data on D15:D8.

And those are the three cases that are possible (A0 high and BHE high doesn't enable any banks, so it doesn't do anything). Note that the lines A19:A1 are the same in all three cases, and they don't change throughout a clock cycle. If the 8086 wants to read a word at addresses 125-126, it can't get it this way, because those two addresses have different bits on A19:A1. It needs to make two reads, as the book describes.

Your book is considering only A19:A1 as being part of "the address", and A0 as being strictly an enable line, which means it always considers bus addresses to be even. This is basically the truth, since the even and odd bytes of a word are addressed as a unit, but it doesn't really agree with the Intel-approved terminology.

  • \$\begingroup\$ I assume the difference between the three cases is only really relevant when it comes to writes? (except maybe for some tiny power saving if you only read the byte you actually need) \$\endgroup\$
    – Michael
    Commented May 10, 2020 at 9:11
  • \$\begingroup\$ @Michael mostly yes. I suppose a memory-mapped device could decide to do something funny, though. I stuck with reads because that was the example in the question. \$\endgroup\$
    – hobbs
    Commented May 10, 2020 at 9:50

In fact the 8086 does it exactly the latter way you describe, and it has to use two memory cycles to do it.

To access word from address 125, the CPU puts 125 on the address bus. Since it is an odd address and only high byte is needed from this address, address A0 bit will be 1 and BHE is active, so only high byte of memory responds. Next, the address 126 is put on the bus, and since it is an even address, and only low byte is requested, A0 will be low and BHE inactive, so only low byte of memory responds. Now a full word has been read from two concecutive addresses, because it could not be read as a 16-bit access from single even address, where A0 bit would be 0 and BHE active so both low and high bytes are returned.

  • \$\begingroup\$ So, am I wrong about the part where I mentioned that the CPU puts 124 on the address bus instead of 125? The book "The Art of assembly language" mentions that 8086 puts only even addresses on the address bus. \$\endgroup\$ Commented May 9, 2020 at 15:22
  • \$\begingroup\$ Where in the book it says so? Which edition of the book? It really does not matter how the CPU does it, the effect is same though, even if it did put address 124 on the bus. Besides there usually is a lot of logic circuitry or chipset between CPU and memory so what the CPU signals to do may change in the chipset. \$\endgroup\$
    – Justme
    Commented May 9, 2020 at 15:52
  • \$\begingroup\$ It says so in the last paragraph on Page 90. You can find the book at this link : bit.ly/2WKxnKu \$\endgroup\$ Commented May 9, 2020 at 15:56
  • 1
    \$\begingroup\$ Well, the book is wrong on that exact detail, but it still does not change the concept how it must operate. Why the book says that, might be due to the fact that when e.g. a 286 CPU fetches opcodes, it always uses even addresses to fetch two opcode bytes at a time, it will just ignore one byte if the opcode fetch happens to odd address. \$\endgroup\$
    – Justme
    Commented May 9, 2020 at 16:20

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