# How to use global clock in VHDL

I'm teaching myself CPLD programming using a development board with an Altera MAX II EPM240.

After learning how to make a 4-bit digital counter in VHDL using clock/reset inputs, I'd like to use the onboard 50MHz oscillator wired to pin 62. I understand it is fed to the Global Clock Network, but how do I wire it to an input of my VHDL design? (in my case CLOCK)

entity Foo is
port(
CLOCK: in std_logic;
LED_0: out std_logic
);
end Foo;

architecture rtl of Foo is
begin
LED_0 <= CLOCK;
end rtl;


I know I can assign I/O pins to my design with the Pin Planner tool in Quartus II 13.1. I tried assigning pin 62 to the CLOCK signal, but I see no visible output to LED_0 (one of the onboard LEDs). I'd expect to be half-lit, but it's always on. I suppose it's because I'm now trying to use pin 62 as a regular I/O, which is not what I want.

The datasheet mentions LAB column clocks, and signals like labclk1 or labclkena1, but I have no idea how to reference them. As far as I can tell, the signal names I define in my VHDL design aren't related to any internal signals of the chip it will run on.

How do I tell (either in VHDL or with the Quartus tools) that I want one of my input signals to be connected to one of the Global Clock Network clocks?

• I would try actually using it as a clock; i.e. clock a register or a counter from it. (Then use the last bit of the counter to drive the LED). That gives the tools a chance to identify it as a clock and route it appropriately. May 9 '20 at 10:49
• You ought to be able to #include an Altera Max library into your VHDL design to give you access to the specific chip resources. Good practice is to have two VHDL sources, one that is hardware agnostic with a generic interface and ideally contains most of the interesting parts, and a hardware specific harness that matches the resources and the generic signals. This way, if you want to retarget the design, most of the source stays the same, and only the hardware facing part needs rewriting. May 9 '20 at 13:32
• @BrianDrummond I was skeptical at first, but after clearing all the assignments the fitter did actually assign my CLOCK signal to one of the global clocks. Adding a clock divider did also make the output way more visible. If you convert your comment to an answer I'll accept it. May 9 '20 at 16:46