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I keep on getting an error of multiple source. Here is my code for the testbench I am making.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparator_testbench is
end comparator_testbench;

architecture behavior of comparator_testbench is
  --define the max delay for the DUT
  constant MAX_DELAY : time := 20 ns;

  -- declare a constant to hold an array of input values
  type input_value_array is array (0 to 9) of STD_LOGIC_VECTOR(7 downto 0);
  constant in1_sig_values : input_value_array := ("00000000","00000001","00010010","00000100","00001000",
                          "00010000","00100000","01000000","10000000","00000011"); 
                          ---------------------------------------------------
  constant in2_sig_values : input_value_array := ("00010000","00100000","00010010","10000000","00000011",
                          "00000000","00000001","00000010","00000100","00001000");
                          ---------------------------------------------------
  constant in3_sig_values : input_value_array := ("00010000","00000001","0000001","00000001","01000000",
                          "00000010","10000000","00000011","00000100","00001000");
                          ---------------------------------------------------
  constant in4_sig_values : input_value_array := ("00000010","00110101","0000001","00000001","01000000",
                          "00000010","10000000","00000011","00000100","00001000");

  -- define signals that connect to DUT
  signal input_1_sig : STD_LOGIC_VECTOR(7 downto 0);
  signal input_2_sig : STD_LOGIC_VECTOR(7 downto 0);
  signal input_3_sig : STD_LOGIC_VECTOR(7 downto 0);
  signal input_4_sig : STD_LOGIC_VECTOR(7 downto 0);
  signal min_index_sig_2: integer;
  signal max_index_sig_2: integer;

  begin
  
    -- this is the process that will generate the inputs
    stimulus : process
      begin
    for i in 0 to 9 loop
      input_1_sig <= in1_sig_values(i);
      input_2_sig <= in2_sig_values(i);
      input_3_sig <= in3_sig_values(i);
      input_4_sig <= in4_sig_values(i);
      min_index_sig_2 <= i;
      max_index_sig_2 <= i;
          wait for MAX_DELAY; -- do nothing right now
        end loop;
    wait;
    end process stimulus;

    -- this is the component instantiation for the
    -- DUT - the device we are testing
    DUT : entity work.comparator(behavioral)
      port map(input_1 => input_1_sig, input_2=>input_2_sig,
               input_3 => input_3_sig, input_4=>input_4_sig,
           min_index => min_index_sig_2, max_index => max_index_sig_2 );

end behavior;

Here is the code for the comparator file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparator is

Port (input_1 : in STD_LOGIC_VECTOR (7 downto 0); -- Input stream
      input_2 : in STD_LOGIC_VECTOR (7 downto 0); -- Input stream
      input_3 : in STD_LOGIC_VECTOR (7 downto 0); -- Input stream
      input_4 : in STD_LOGIC_VECTOR (7 downto 0); -- Input stream
      min_index : out integer;            -- Index
      max_index : out integer;
      MAX_OUT   : out STD_LOGIC_VECTOR (7 downto 0);
      MIN_OUT : out STD_LOGIC_VECTOR (7 downto 0));-- The minimum of the stream 
       
end comparator;

architecture Behavioral of comparator is
    signal min : std_logic_vector(7 downto 0):="11111111";
    signal max : std_logic_vector(7 downto 0):="00000000";
    signal min_index_sig : integer;
    signal max_index_sig : integer;
begin

    find_min : process
    begin
        
        if ((input_1 <= input_2) and (input_1 <= input_3) and(input_1 <= input_4)) then
        min <= input_1;
        min_index_sig <= min_index_sig;
        elsif ((input_2 <= input_1)and(input_2<=input_3)and(input_2<=input_4)) then
        min <= input_2;
        min_index_sig <= min_index_sig;
        elsif ((input_3 <= input_1)and(input_3<=input_2)and(input_3<=input_4)) then
        min <= input_3;
        min_index_sig <= min_index_sig;
        elsif ((input_4 <= input_1)and(input_4<=input_3)and(input_4<=input_2)) then
            min <= input_4;
        min_index_sig <= min_index_sig;
            else
            min <=min;
        end if;
        wait;
    end process find_min;
    MIN_OUT <= min;
    min_index<=min_index_sig;
    -------------------
    find_max : process
    begin
        --if ( input > max ) then
        --max <= input;
        --max_index_sig <= max_index_sig;
        --else
        --max <= max;
        --end if;
        if ((input_1 >= input_2)and(input_1>=input_3)and(input_1>=input_4)) then
        max <= input_1;
        max_index_sig <= max_index_sig;
        elsif ((input_2 >= input_1)and(input_2>=input_3)and(input_2>=input_4)) then
        max <= input_2;
        max_index_sig <= max_index_sig;
        elsif ((input_3 >= input_1)and(input_3>=input_2)and(input_3>=input_4)) then
        max <= input_3;
        max_index_sig <= max_index_sig;
        elsif ((input_4 >= input_1)and(input_4>=input_3)and(input_4>=input_2)) then
            max <= input_4;
            max_index_sig <= max_index_sig;
        --include max index sig in testbench
        
            else
            max <=max;
        end if;
        wait;
    end process find_max;
    MAX_OUT <= max;
    max_index<=max_index_sig;
    
end Behavioral;

Here is a screenshot of the error I am getting:

enter image description here

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3
  • \$\begingroup\$ Did you look at the signal names specified at the lines specified in the error message? min_index_sig_2 <= i; max_index_sig_2 <= i; only shows up in one place so maybe the for loop has something to do with it. \$\endgroup\$
    – DKNguyen
    Commented May 10, 2020 at 0:56
  • \$\begingroup\$ I did but that didn't help. I don't understand what is wrong with the signal names \$\endgroup\$ Commented May 10, 2020 at 0:56
  • \$\begingroup\$ The message tells you precisely what's wrong. You are driving these signals at lines 21 and 22, and later at lines32,33 you connect them to output ports which also drive them. You don't want to do that. What you most likely want to do is drive another signal at line 21,22, and then compare teh two copies (one from the stim process, the other from the DUT, and report if they are different. \$\endgroup\$
    – user16324
    Commented May 10, 2020 at 9:41

1 Answer 1

1
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Alll the for loops exist and run at the same time and compete to assign:

min_index_sig_2 <= i;

max_index_sig_2 <= i;

Why do you have multiple loop iterations assigning things simultaneously to the same signals?

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3
  • \$\begingroup\$ How can I fix this \$\endgroup\$ Commented May 10, 2020 at 0:59
  • \$\begingroup\$ actually...you do that with all signals in that loop. why is it not complaining about the others? This isnt software where each loop iteration runs one after another. the loop here defines a separate circuit so you dont have to type as much and everything in that for loop exists al the time and is trying to run at the same time \$\endgroup\$
    – DKNguyen
    Commented May 10, 2020 at 1:10
  • \$\begingroup\$ you need to completely restructure your test stimulus so things run in a sequence \$\endgroup\$
    – DKNguyen
    Commented May 10, 2020 at 1:18

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