I'm teaching myself VHDL using this MAX II CPLD board.

I designed a frequency divider and 4-bit counter in VHDL using the onboard 50MHz oscillator. It seemed to work as the onboard LEDs are flashing in the right way, but I noticed that they flash slower when my hand is near the chip or the onboard crystal oscillator.

The oscillator is in a 4-pin metal package. It has markings 50.000 and e552. It's X1 in the board; pics are in the above link. Not sure if it contains a crystal or uses some other technology.

Some pictures of the board, especially the area between the CPLD and the oscillator. I think the clock goes from X1 through R5, then to the bottom side, then back to the top side, then to pin 62. Pin 62 is the only pin on the right side of the chip that doesn't go to the pin header at the right side of the board, roughly in the middle of the MAX II label.

The CPLD board, top side

The CPLD board, bottom side

It might be a problem of floating inputs, but the counter doesn't have any input pins (not even a reset!). I don't need to tie all unused 72 I/O pins to ground, do I? Here is the VHDL:

entity SpdifTest is
    CLOCK: in std_logic;
    LED: out std_logic_vector(3 downto 0)
end SpdifTest;

architecture rtl of SpdifTest is
    signal output : std_logic_vector(3 downto 0);
    signal count : std_logic_vector ( 23 downto 0 );

        if (rising_edge(CLOCK)) then
            count <= count+1;
            output <= count(23 downto 20);
        end if;
        LED <= not output;
    end process;
end rtl;

Here are the pin assignments in Tcl (pin 62 is the clock):

set_location_assignment PIN_62 -to CLOCK
set_location_assignment PIN_40 -to LED[0]
set_location_assignment PIN_43 -to LED[3]
set_location_assignment PIN_42 -to LED[2]
set_location_assignment PIN_41 -to LED[1]

Is there something else I missed, or maybe the board is faulty? The same thing happens with a similar board (with EPM570 instead of EPM240).

  • 2
    \$\begingroup\$ Don't know what type of oscillator it is, but it could be that you are adding capacitance or something that slows down the oscillator. But it would seem unlikely in the case of a circuit with a crystal. \$\endgroup\$
    – Joren Vaes
    May 10, 2020 at 9:41
  • \$\begingroup\$ Thanks, I added details about the oscillator. \$\endgroup\$ May 10, 2020 at 9:46
  • \$\begingroup\$ Odd. Is the oscillator's case grounded? \$\endgroup\$
    – user16324
    May 10, 2020 at 10:01
  • \$\begingroup\$ @BrianDrummond it is. Did a continuity check. \$\endgroup\$ May 10, 2020 at 10:15
  • 1
    \$\begingroup\$ Sounds layout related. Please show related parts. \$\endgroup\$
    – winny
    May 10, 2020 at 14:21

1 Answer 1


While following the clock trace in the layout (thanks @winny to point me in the right direction) I realized that the oscillator was connected to pin 12 of the chip, not pin 62.

The reason I was focusing on pin 62 is that I did a continuity check between the X1 pins and the CPLD. I was probably fooled by a common ground connection. I should have carefully followed X1 traces and found the 33 ohm resistor in series, then followed the trace up to pin 12.

And I suppose the reason pin 62 was still kinda working is because it was a floating pin picking up some of the signal from the nearby clock input.

Of course none of this could have happened if I had a board schematic or some other documentation, but the website (www.ourfpga.com) seems to be dead.


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