I have a few questions concerning a input adapter load switch schematic for a battery charger IC (bq25780S). I posted a screeshot of this part of the schematic from the reference design (BQ24780S Reference below and marked the relevant part in yellow.

ACDRV is the charge pump output for the N-FETs $$\Q1\$$ and $$\Q2\$$. CMSRC is the charge pump input for ACDRV. Note that CSD17308Q3 are used for $$\Q1\$$ and $$\Q2\$$. I understand that $$\C13\$$ is used to soft-start $$\Q1\$$ and $$\Q2\$$, and $$\R12\$$ and $$\R13\$$ will limit inrush current of gate capacitances.

What I do not understand:

1. According to datasheet the ACDRV and CMSRC pins of the IC need $$\R12\$$ and $$\R13\$$ to "limit the current due to the ESD diode of these pins". Why do ESD diodes, that usually "clamp" high voltage peaks to ground, need inrush current resistors for FET switching?

2. Is $$\C12\$$ used for prevention of self-turn on of FET during hot adapter pulgging? If yes, why can't I just use a FET with a high enough $$\C_{GS}\$$ compared to $$\C_{GD}\$$?

3. What is the purpose of $$\R7\$$? And why can't I just use $$\R1\$$ or $$\R2\$$ (3.9 Ohm) instead to reduce unique component count?

1) R12 and R13 limit the inrush when the adapter is reversed. In that case, V_IN is negative with respect to ground. Q7 turns ON, shorting G-S of Q1 and Q2, ensuring they're OFF. Alas, the "body diode" of Q1 is now ON, connecting the (negative) V_IN to the IC ACDRV and/or CMSRC pins -- in basically current-unlimited negative polarity (with respect to ground). So, if e.g. ACDRV had a safety diode that normally would shunt more-negative-than-ground -- now that (tiny) diode is 100% forward biased with ump-teen volts across it and nothing to really dampen that current. "So, the smoke will escape" and we all know what that means :) Hence the need for R12/R13.

For 2) I can't imagine. The datasheet goes into a lot about "voltage spikes when the adapter is plugged in" although I can't see why C1 would make any difference. It's not mentioned in the datasheet.

For 3) Again I can't imagine. This is a MOSFET gate with megohms or gigohms of input Z. Yes, considerable capacitance, but 4.7Ω? Why not the same for the other MOSFET? Crazy stuff.

Hope this "1/3 of an answer" helps.

• It may be that C1, R7 aid in compensating the loop under certain conditions of Q1 being ON, or OFF, or transitioning between the two. There is a feedback loop from ACCDRV thru R12, thru C1 (but loaded by Q1's gate) thru R3/R4, back to the IC. Perhaps R7, so small as it is, still is enough to add a necessary zero to the loop since it (I guess) isolates Q1's considerable gate capacitance. – Atomique May 10 at 21:18
• In the datasheet it is meantinoned that CGS must be 40 x CGD, which would fit to the values of C12 and C13. Could this be the reason? And maybe R7 is there to turn on Q1 slgithly later then Q2 to avoid load current over Q2's body diode? – F. Heisenberg May 10 at 21:26
• and R12 and R13 do also limit the inrush current when switching the FETs on, correct? – F. Heisenberg May 10 at 21:31

In my experience (and I realise this is opinion, so take it with a pinch of salt) reference designs vary widely in their design excellence. Some are clearly the result of comprehensive design, testing and value engineering, while others seem to have been done by a work experience student. In general, they all seem to be more complex than designs actually on the market. So it may be that they include features or protections that don't survive the commercial imperatives of going to market.