# How to find Input capacitance and output resistance of a CMOS circuit with spice

I have a 2-input NAND gate spice netlist (generated from a Tanner Ledit layout) where I have to find each input's capacitance and the output resistance. I am to use a 1nF load capacitor and a 10 Kohm for the calculations. I honestly have no idea how to do this using spice and could really use some help getting started. Here is the netlist:

*** Extration Obtained


.include Model.txt

• NODE NAME ALIASES
• 1 = Vdd (23.999,44)
• 2 = Gnd (28.999,0.5)
• 3 = Nand_out (20.999,21)
• 4 = A (46.999,19.5)
• 5 = B (49.999,24)

M1 6 4 3 2 NMOS L=2u W=10u AD=70p PD=34u AS=55p PS=31u * M1 DRAIN GATE SOURCE BULK (30.5 5 32.5 15) M2 2 5 6 2 NMOS L=2u W=10u AD=70p PD=36u AS=70p PS=34u * M2 DRAIN GATE SOURCE BULK (39.5 5 41.5 15) M3 1 4 3 1 PMOS L=2u W=10u AD=80p PD=38u AS=110p PS=62u * M3 DRAIN GATE SOURCE BULK (30.5 27 32.5 37) M4 3 5 1 1 PMOS L=2u W=10u AD=110p PD=62u AS=80p PS=38u * M4 DRAIN GATE SOURCE BULK (39.5 27 41.5 37)

• Total Nodes: 6
• Total Elements: 4
• Extract Elapsed Time: 0 seconds .END

Any help would be appreciated!

The input capacitance will vary, perhaps greatly, as the input voltage slews between the rails.

Similarly the output resistance, though not greatly (maybe 2:1), as the input voltage slews between the rails.

By measuring the input (transient) current during slewing, you can compute the Cin.

Note the heavy Cload will slow the output and thus reduce the charge demanded across the FETs C_gate_drain, thus artificially lowering the Cin.

Foe Rout, remove the Cload and Rload, run a input transient at risetime of your chosing, while driving the output with 100 uA sinusoid current source.

As mentioned by @analogsystemsrf, the capacitance varies, so a .TRAN analysis will be a bit more involved, but since this is SPICE world you can measure it easily in .AC by adding a current source at the input with ac 1 as value and the impedance will be Vin/Iin. Since Iin is unity, you can read the value of the impedance in Volts as Vin:

I didn't use your models, or your configuration (you didn't provide it), or your load (same), this is just for exemplification. The analysis goes from 1 MHz to 1 THz because the capacitances are so small and there are resistances about that cause that zero to appear. The capacitance will be determined by the slope of the magnitude. Also, the output capacitance influences the input, and you can see that the phase after 1 GHz is not quite so smooth. Since the values are not fixed, it leaves room for experimentation, whether you want the input impedance analyzed in open configuration (Vdd disconnected, no load), or statically (as it is now), or dynamically (you'll need .TRAN for that, slightly more complicated).

(answer to the comment) If what you need is a dynamic analysis, here is a possible setup for finding out how the input impedance varies with input voltage:

The ramp at the input is the usual suspect in determining the transfer function. A pulsed input can also be used, but it tends to complicate things.

However, given your description in the OP, the input/output characteristics are usually found by doing an .AC analysis. The resulting values are what you see in the tables in the datasheets. Their dynamic variance is based on that initial value, and it's depicted in graphs according to whatever criteria need to be met. The ramp here was used for the lack of other descriptions.

For the sake of completion, if the ramp at the input has a unity dV/dt, then its derivative will be 1 and the current through the gate will be directly proportional to the capacitance:

If you consider this graph as an example, which value from it would you use in a datasheet as input capacitance?

I never said the gate capacitance is not a function of voltage, in fact, I said, several times, that it gets more complicated if you choose to analyze it in time domain vs frequency. Do note that this is a . I never said there are datasheets (a word nicely emboldened) for the transistors composing the gates, I said datasheets show Ciss, as an example, which is specific to MOS transistors. You keep saying that you need to determine

the effective capacitance seen by a driver as the gate input voltage changes from Vss to Vdd

while referring to a specific value representing a range of use cases, but that's exactly what I did: determine one value, but I never said one measurement. This is also valid for your saying that I

keep trying to treat the problem as a transfer-function, frequency response question

There's no transfer function involved as the linked answer shows: it's a simple calculation based on a simple .AC analysis. And, BTW, saying that

Matching exactly the value in the .model file should be a red flag. We know that the capacitance varies with voltage, but the values in the .model file are obviously constant.

would warrant a long stare. Yes, it's constant, but, as I said, that value serves as calculations for any dynamic regime. You seem to overlook the fact that, internally, the .model makes use of that value for its equations which vary the capacitance dynamically.

What's more, when I said that using a unity dV/dt ramp at the input will give the exact value of the capacitance as a function of the input, you said it's not true, even though not only I posted my 3rd picture in this answer, but also linked to this picture, showing why it's not so. Here is, again, what happens if you calculate the exact value of the capacitance with an .AC analysis and a sweep of input's DC:

{x} is the DC level and the capacitance is measured on the fixed slope, @1 MHz, because that point is surely dominated by the gate's capacitance. Since the ac source is unity, the reverse of the current though the gate displays the impedance (see waveform label), which can be used to calculate the capacitance (see the .meas). Because {x} is .stepped, the values for the measured c can be plotted and they are displayed in the 3rd window. What a coincidence, the graph looks very similar to the one in my 3rd picture. In fact, I'd say they are exact within float precision, for the displayed points. This not only proves that what I said about the unity dV/dt is true (as expected for a physical phenomenon), but also that your contradictions are wrong.

If you are to actually determine a value (I avoided this, reasons later on), you would use the average of two values, for ON and OFF:

Measurement: c
step  mag(i(v2))/2/pi/1meg    at
1  (1.42605e-10,0) 1e+06
2  (3.92237e-10,0) 1e+06


Their average is ~267.5 pF. But the gate has a transition region, and the gate @6 V is 647.918 pF. If you make the average now, you get ~394 pF. And if you make the average of all that nonlinearity, you get what you see in the picture, ~463 pF. This would be the equivalent of what you said about integrating the values. But the highest value is not at the middle, and its value is quite large there. Also, since it's switching, the edges will not have the same weights as the ON/OFF, so how do you determine the weighting? It turns out that you can live with an unweighted average between the two maximum values. Here is a document showing that the determination for the input capacitance is about the same procedure.

You said your choice would be using a current source and measuring the time it takes to reach Vdd. I said it's not reliable, and here's why:

It takes ~5.61 s to reach ~12 V. The resulting value would be (1 nA * 5.61 s)/(12 V) = 467.5 pF. Compare this with the 463 pF above. This average means considering equal weights for ON, OFF, and transitions, which is hardly the case (also mentioned above). If it is, the ON/OFF times would be about the same, or comparable to the transitions, and the dissipated power would be prohibitive. Using this value would also mean overstating by a factor of almost 2, confusing the user.

But this should have been the conclusion OP would have reached given my words at the ending of the 1st edit. I never said "that value, right there, is the only one you'll need". I said you can use this way to measure, easily since it's SPICE, leaving room for OP to think for him/herself. This was "just for exemplification". It's also the reason I made an INV, not (N)AND, to avoid being explicit. But it's a homework, not a quest for a datasheet, and even datasheets display only one value for the input capacitance.

And, finally, when I said we were talking about different things, I meant that while I said that you can measure the input capacitance with .AC and unity dV/dt, you replied saying that the capacitance is a function of voltage.

• Also see this. – a concerned citizen May 11 at 7:22
• I would be suspicious of using an .AC analysis. My understanding is that an .AC analysis assumes that the circuit is linear but we know that the input capacitance of the gate is a non-linear function of voltage. My preference is to use a constant current and measure the time it takes for the input to swing from Vss to Vdd. – Elliot Alderson May 11 at 15:01
• Also, you must make sure that your ac source voltage swing is over the full power supply voltage range and does not exceed that range. Pretty difficult if your source is an ac current. – Elliot Alderson May 11 at 15:02
• @ElliotAlderson Then what you want is a dynamic analysis (as mentioned in the last phrase). I'll update my answer to include a possible setup, but an.AC analysis like the one I proposed are pretty standard for finding out static values. – a concerned citizen May 11 at 15:08
• @ElliotAlderson If you look in the link I posted, you'll see that it matches exactly the value from the .model. That value serves as a basis for any dynamic variance of it. To me, it does sound like you're overcomplicating a bit, but you're the one who knows best what you need. Just one question: suppose you manage to find a varying graph for the input capacitance, and the gate you have is meant for a datasheet; what value from it will you use in the tables? – a concerned citizen May 11 at 15:28