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I'm working with STM32F411RE but I presume the problem is the same for any STM32F, and possibly others.

I couldn't find in the reference manual whether or not the RTC is halted during a debug session. For any other IPs, including those clocked with different clock sources like the watchdog IP, it's clearly mentioned that debug halting is configurable or at least the behavior is fixed and given.

What about the RTC ?

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  • \$\begingroup\$ I'm currently developing on a STM32F427 and on this device I haven't observed any effect on the RTC when debugging. It's clocked by its own separate crystal and powered by its own battery, and the config settings are kept 'safe' behind an unlocking sequence. Enabling/disabling the peripheral clock to the RTC module has no effect on the RTC's counter or anything else in the domain powered by the RTC battery and clocked by the RTC crystal. \$\endgroup\$
    – brhans
    Commented May 11, 2020 at 11:31
  • \$\begingroup\$ My problem is if I break at some point will the RTC still count ? I think the answer is yes but I would like a reliable source for this. \$\endgroup\$
    – Welgriv
    Commented May 11, 2020 at 11:34
  • \$\begingroup\$ The answer to that is a definite 'yes'. Stopping the CPU has no effect at all on the RTC's counter - it continues to count since it has it's own dedicated clock source (the 32kHz crystal). \$\endgroup\$
    – brhans
    Commented May 11, 2020 at 11:38
  • \$\begingroup\$ If you read carefully my question you'll see that I note and I know that: IWDG and WWDG also have their "own" clock source and can explicitly be altered during debug. Debug does not act only on the CPU since outside-CPU-timers on APB bus can also be altered during debug. (Btw, LSI RC clock can be selected as the RTC clock source and is not generated by a crystal. It is on the chip and probably a basic oscillator) \$\endgroup\$
    – Welgriv
    Commented May 11, 2020 at 12:29

1 Answer 1

Reset to default
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Found the solution: The STM32F411 have a register on the debug IP controlling the halted state of the RTC. Register is

Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)

Reset state is 0. The field is

Bit 10 DBG_RTC_STOP: RTC stopped when Core is halted

0: The RTC counter clock continues even if the core is halted

1: The RTC counter clock is stopped when the core is halted

Reference manual p 830

My mistake was to not search in the debug IP part of the documentation but in the RTC part.

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