Conducted Emissions of EV Charging Electronics

Question

I'm building an AC-charging device for electric vehicles (the standard calls it an "ICCPD" or an "In Cable Control and Protective Device") and I'm facing some EMC issues due to the PWM Signal on the CP-wire.

Background:

The charging device is connected to the vehicle via the type-2 connector. The cable to the EV looks like this and is approx. 5-10m long:

The CP wire is used for the communication between the vehicle and the ICCPD. Basically it carries a PWM signal and the duty cycle indicates the maximum charging current. The frequency, amplitude and rise-time is defined in the standard.

• f=1kHz
• positive amplitude = 6/9/12V (relative to PE)
• negative amplitude = -12V (relative to PE)
• rise/fall time = <2us

Problem description:

The following figure shows the conduced emissions with PWM signal ON (turquoise) and without PWM signal...const +12V (blue) measured on the neutral line. Cable length was 9m. Measured with Rohde&Schwarz Precompliance test equipment (HMS-X and HM6050-2).

Question:

Is there any way to reduce the conducted emissions due to the CP-Signal?

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Update 1:

Reducing the cable length and/or shielding the CP-wire is not possible.

Update 2:

According to my understanding the equivalent schematic looks like this!? And the Problem is the parasitic capacitance between CP and N (Neutral), which is approx. 60pF/m based on the dimensions.

Update 3:

conduced emissions according to Andy's suggestion/ thought experiment:

• Turquoise line: PWM Signal on CP wire inside the cable
• Blue Line: PWM signal connected to a separated wire (no PWM signal on CP wire in the cable)

Answer 1

The first null, of the second/green plot, is at 1.2MHz.

From what I've seen on Spectrum Analyzers (and in Fourier modeling), the first null is at 1/Trise.

So yes ----- If you can slow down the edge, give that a try.

How you chose to DAMPEN the filter may be key. Experiment with parallel or series resistors with the inductor.

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EDIT:

Install a "L" or "T" or "PI" filter, with cutoff at 1MHz (about 0.5uS Trise).

The idea is to weaken the correlation of the "fast edge" with the FFT algorithm inside the R&S boxes.

By converting a perfect RAMP edge into an "ESS" edge, having sort attack and soft delay edges before and after the "rise time", the correlation will be reduced.